bug fixes from Fujitsu (bug 37)
---------------------------------------------------------- bug 37 Ttile: Sending side is as follows. rar[3] = (((mcs&0x7)<<5)) | ((TPC&7)<<2) | ((ULdelay&1)<<1) | (cqireq&1); So, 2 bit shift looks correct. Bug Location: ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>3)&7;//rar->TPC; ----------------------------------------------------------
This commit is contained in:
@@ -238,7 +238,7 @@ int generate_ue_ulsch_params_from_rar(PHY_VARS_UE *ue,
|
||||
|
||||
|
||||
|
||||
ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>3)&7;//rar->TPC;
|
||||
ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>2)&7;//rar->TPC;
|
||||
|
||||
rballoc = (((uint16_t)(rar[1]&7))<<7)|(rar[2]>>1);
|
||||
cqireq=rar[3]&1;
|
||||
|
||||
Reference in New Issue
Block a user