Merge branch 'NR_RRC_harq_newdcipdu' into NR_RRC_harq
This commit is contained in:
Francesco Mani
@@ -517,11 +517,44 @@ int get_num_dmrs(uint16_t dmrs_mask ) {
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return(num_dmrs);
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}
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uint16_t nr_dci_size(nr_dci_format_t format,
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// Table 5.1.2.2.1-1 38.214
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uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) {
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AssertFatal(bwp_size<276,"BWP Size > 275\n");
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if (bwp_size < 37) return (rbg_size_config ? 4 : 2);
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if (bwp_size < 73) return (rbg_size_config ? 8 : 4);
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if (bwp_size < 145) return (rbg_size_config ? 16 : 8);
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if (bwp_size < 276) return 16;
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}
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uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
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uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config);
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return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size);
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}
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uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) {
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uint8_t nbitsA, nbitsB, nbits = 0;
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if (typeA != NULL) nbitsA = (typeA->choice.setup->maxLength[0]==0) ? 4 : 5;
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if (typeB != NULL) nbitsB = (typeB->choice.setup->maxLength[0]==0) ? 5 : 6;
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if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB;
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return nbits;
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}
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uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
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dci_pdu_rel15_t *dci_pdu,
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nr_dci_format_t format,
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nr_rnti_type_t rnti_type,
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uint16_t N_RB) {
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NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup;
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uint16_t size = 0;
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int bwp_id = 1;
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NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
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switch(format) {
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/*Only sizes for 0_0 and 1_0 are correct at the moment*/
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@@ -529,7 +562,7 @@ uint16_t nr_dci_size(nr_dci_format_t format,
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/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
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size += 20;
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size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated
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size += nr_dci_size(NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size
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size += nr_dci_size(secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size
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// UL/SUL indicator assumed to be 0
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break;
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@@ -562,29 +595,112 @@ uint16_t nr_dci_size(nr_dci_format_t format,
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break;
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case NR_DL_DCI_FORMAT_1_1:
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// Format identifier
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size = 1;
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// Carrier indicator
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size += 1; // Format identifier
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if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
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dci_pdu->carrier_indicator.nbits=3;
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size += dci_pdu->carrier_indicator.nbits;
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}
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// BWP Indicator
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uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
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dci_pdu->bwp_indicator.nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp)));
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size += dci_pdu->bwp_indicator.nbits;
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// Freq domain assignment
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long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size;
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uint16_t numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
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NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
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rbg_size_config);
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if (pdsch_config->resourceAllocation == 0)
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dci_pdu->frequency_domain_assignment.nbits = numRBG;
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else if (pdsch_config->resourceAllocation == 1)
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dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
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else
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dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
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size += dci_pdu->frequency_domain_assignment.nbits;
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// Time domain assignment
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NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_timeDomList = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
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int num_entries;
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if (pdsch_timeDomList != NULL)
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num_entries = pdsch_timeDomList->list.count;
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else
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num_entries = 16; // num of entries in default table
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dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries));
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size += dci_pdu->time_domain_assignment.nbits;
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// VRB to PRB mapping
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if (pdsch_config->resourceAllocation == 1) {
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dci_pdu->vrb_to_prb_mapping.nbits = 1;
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size += dci_pdu->vrb_to_prb_mapping.nbits;
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}
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// PRB bundling size indicator
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if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) {
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dci_pdu->prb_bundling_size_indicator.nbits = 1;
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size += dci_pdu->prb_bundling_size_indicator.nbits;
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}
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// Rate matching indicator
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NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1;
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NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2;
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if ((group1 != NULL) && (group2 != NULL))
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dci_pdu->rate_matching_indicator.nbits = 2;
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if ((group1 != NULL) != (group2 != NULL))
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dci_pdu->rate_matching_indicator.nbits = 1;
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size += dci_pdu->rate_matching_indicator.nbits;
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// ZP CSI-RS trigger
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/// TB1- MCS 5, NDI 1, RV 2
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uint8_t nZP = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count;
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dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1));
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size += dci_pdu->zp_csi_rs_trigger.nbits;
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// TB1- MCS 5, NDI 1, RV 2
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size += 8;
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// TB2
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size += 4 ; // HARQ PID
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long *maxCWperDCI = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI;
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if ((maxCWperDCI != NULL) && (*maxCWperDCI == 2)) {
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size += 8;
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}
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// HARQ PID
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size += 4;
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// DAI
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size += 2; // TPC PUCCH
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size += 3; // PUCCH resource indicator
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size += 3; // PDSCH to HARQ timing indicator
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if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells
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dci_pdu->dai[0].nbits = 4;
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size += dci_pdu->dai[0].nbits;
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}
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// TPC PUCCH
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size += 2;
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// PUCCH resource indicator
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size += 3;
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// PDSCH to HARQ timing indicator
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uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count;
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dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I));
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size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits;
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// Antenna ports
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NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA;
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NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB;
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dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB);
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size += dci_pdu->antenna_ports.nbits;
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// Tx Config Indication
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size += 2; // SRS request
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long *isTciEnable = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI;
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if (isTciEnable != NULL) {
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dci_pdu->transmission_configuration_indication.nbits = 3;
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size += dci_pdu->transmission_configuration_indication.nbits;
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}
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// SRS request
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if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL)
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dci_pdu->srs_request.nbits = 2;
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else
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dci_pdu->srs_request.nbits = 3;
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size += dci_pdu->srs_request.nbits;
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// CBGTI
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uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2;
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long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI;
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uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc;
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dci_pdu->cbgti.nbits = maxCBGperTB * maxCW;
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size += dci_pdu->cbgti.nbits;
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// CBGFI
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size += 1; // DMRS sequence init
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if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) {
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dci_pdu->cbgfi.nbits = 1;
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size += dci_pdu->cbgfi.nbits;
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}
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// DMRS sequence init
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size += 1;
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break;
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case NR_DL_DCI_FORMAT_2_0:
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@@ -341,13 +341,13 @@ int configure_fapi_dl_pdu(int Mod_idP,
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scc->dmrs_TypeA_Position,
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pdsch_pdu_rel15->NrOfSymbols);
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dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
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dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15));
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dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
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dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
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pdsch_pdu_rel15->rbStart,
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NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
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dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV;
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dci_pdu_rel15[0].vrb_to_prb_mapping = 1;
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dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV;
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dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1;
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dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0];
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dci_pdu_rel15[0].tb_scaling = 1;
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@@ -356,18 +356,19 @@ int configure_fapi_dl_pdu(int Mod_idP,
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dci_pdu_rel15[0].ndi = 1;
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dci_pdu_rel15[0].rv = 0;
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dci_pdu_rel15[0].harq_pid = 0;
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dci_pdu_rel15[0].dai = (pucch_sched->dai_c-1)&3;
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dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3;
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dci_pdu_rel15[0].tpc = 2;
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dci_pdu_rel15[0].pucch_resource_indicator = pucch_sched->resource_indicator;
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dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = pucch_sched->timing_indicator;
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dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator;
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LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
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dci_pdu_rel15[0].frequency_domain_assignment,
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dci_pdu_rel15[0].frequency_domain_assignment.val,
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pdsch_pdu_rel15->rbStart,
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pdsch_pdu_rel15->rbSize,
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NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
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dci_pdu_rel15[0].time_domain_assignment,
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dci_pdu_rel15[0].vrb_to_prb_mapping,
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dci_pdu_rel15[0].time_domain_assignment.val,
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dci_pdu_rel15[0].vrb_to_prb_mapping.val,
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dci_pdu_rel15[0].mcs,
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dci_pdu_rel15[0].tb_scaling,
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dci_pdu_rel15[0].ndi,
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@@ -391,8 +392,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
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dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
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rnti_types[0] = NR_RNTI_C;
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pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
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fill_dci_pdu_rel15(secondaryCellGroup,pdsch_pdu_rel15,pdcch_pdu_rel15,NULL,&dci_pdu_rel15[0],dci_formats,rnti_types);
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fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types);
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LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
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coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
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@@ -424,12 +424,12 @@ int configure_fapi_dl_pdu(int Mod_idP,
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void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) {
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dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
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dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
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pusch_pdu->rb_start,
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NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
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dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV;
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dci_pdu_rel15->frequency_hopping_flag = 0;
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dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV;
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dci_pdu_rel15->frequency_hopping_flag.val = 0;
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dci_pdu_rel15->mcs = 9;
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dci_pdu_rel15->format_indicator = 0;
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@@ -440,9 +440,9 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
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LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
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pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci],
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dci_pdu_rel15->frequency_domain_assignment,
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dci_pdu_rel15->time_domain_assignment,
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dci_pdu_rel15->frequency_hopping_flag,
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dci_pdu_rel15->frequency_domain_assignment.val,
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dci_pdu_rel15->time_domain_assignment.val,
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dci_pdu_rel15->frequency_hopping_flag.val,
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dci_pdu_rel15->mcs,
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dci_pdu_rel15->tpc,
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dci_pdu_rel15->ndi,
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@@ -838,8 +838,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
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config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
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pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
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fill_dci_pdu_rel15(secondaryCellGroup,NULL,pdcch_pdu_rel15,pusch_pdu,&dci_pdu_rel15[0],dci_formats,rnti_types);
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fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types);
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}
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@@ -544,33 +544,23 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
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}
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}
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// TODO: Move the following 3 functions somewhere that UE can also use
|
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// Table 5.1.2.2.1-1 38.214
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uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) {
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AssertFatal(bwp_size<276,"BWP Size > 275\n");
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|
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if (bwp_size < 37) return (rbg_size_config ? 4 : 2);
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if (bwp_size < 73) return (rbg_size_config ? 8 : 4);
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if (bwp_size < 145) return (rbg_size_config ? 16 : 8);
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if (bwp_size < 276) return 16;
|
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}
|
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void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup,
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dci_pdu_rel15_t *dci_pdu_rel15,
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nr_dci_format_t format) {
|
||||
|
||||
uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
|
||||
|
||||
uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config);
|
||||
|
||||
return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size);
|
||||
}
|
||||
|
||||
uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) {
|
||||
|
||||
uint8_t nbitsA, nbitsB, nbits = 0;
|
||||
if (typeA != NULL) nbitsA = (typeA->choise.setup->maxLength[0]==0) ? 4 : 5;
|
||||
if (typeB != NULL) nbitsB = (typeB->choise.setup->maxLength[0]==0) ? 5 : 6;
|
||||
if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB;
|
||||
|
||||
return nbits;
|
||||
switch(format) {
|
||||
case NR_DL_DCI_FORMAT_1_1:
|
||||
//carrier indicator
|
||||
//bwp indicator
|
||||
//vrb to prb mapping
|
||||
//bundling size indicator
|
||||
//rate matching indicator
|
||||
//ZP CSI-RS trigger
|
||||
//dai
|
||||
//antenna ports
|
||||
//srs resource set
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// This function configures pucch pdu fapi structure
|
||||
@@ -758,14 +748,11 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu,
|
||||
}
|
||||
|
||||
void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15,
|
||||
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
|
||||
nfapi_nr_pusch_pdu_t *pusch_pdu,
|
||||
dci_pdu_rel15_t *dci_pdu_rel15,
|
||||
int *dci_formats,
|
||||
int *rnti_types) {
|
||||
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
|
||||
dci_pdu_rel15_t *dci_pdu_rel15,
|
||||
int *dci_formats,
|
||||
int *rnti_types) {
|
||||
|
||||
NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup;
|
||||
uint16_t N_RB = pdcch_pdu_rel15->BWPSize;
|
||||
uint8_t fsize=0, pos=0;
|
||||
uint8_t nbits=0;
|
||||
@@ -773,9 +760,10 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
|
||||
|
||||
uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d];
|
||||
int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],pdcch_pdu_rel15->BWPSize);
|
||||
pdcch_pdu_rel15->PayloadSizeBits[d] = dci_size;
|
||||
AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
|
||||
|
||||
int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d];
|
||||
prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d]);
|
||||
pos = 0;
|
||||
|
||||
/// Payload generation
|
||||
@@ -786,17 +774,17 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// Freq domain assignment
|
||||
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
|
||||
pos=fsize;
|
||||
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_size-pos));
|
||||
LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu);
|
||||
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val&((1<<fsize)-1)) << (dci_size-pos));
|
||||
LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu);
|
||||
// Time domain assignment
|
||||
pos+=4;
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos));
|
||||
LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos));
|
||||
LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
|
||||
// VRB to PRB mapping
|
||||
|
||||
pos++;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos);
|
||||
LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&0x1)<<(dci_size-pos);
|
||||
LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu);
|
||||
// MCS
|
||||
pos+=5;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
|
||||
@@ -817,13 +805,13 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// Freq domain assignment (275rb >> fsize = 16)
|
||||
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
|
||||
pos+=fsize;
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_size-pos));
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<fsize)-1)) << (dci_size-pos));
|
||||
|
||||
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,dci_size-pos,*dci_pdu);
|
||||
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
|
||||
|
||||
uint16_t is_ra = 1;
|
||||
for (int i=0; i<fsize; i++)
|
||||
if (!((dci_pdu_rel15->frequency_domain_assignment>>i)&1)) {
|
||||
if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) {
|
||||
is_ra = 0;
|
||||
break;
|
||||
}
|
||||
@@ -835,7 +823,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
|
||||
// UL/SUL indicator 1 bit
|
||||
pos++;
|
||||
*dci_pdu |= (dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos);
|
||||
*dci_pdu |= (dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos);
|
||||
|
||||
// SS/PBCH index 6 bits
|
||||
pos+=6;
|
||||
@@ -852,13 +840,13 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// Time domain assignment 4bit
|
||||
|
||||
pos+=4;
|
||||
*dci_pdu |= ((dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos));
|
||||
LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,4,dci_size-pos,*dci_pdu);
|
||||
*dci_pdu |= ((dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos));
|
||||
LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu);
|
||||
|
||||
// VRB to PRB mapping 1bit
|
||||
pos++;
|
||||
*dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos);
|
||||
LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu);
|
||||
*dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos);
|
||||
LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu);
|
||||
|
||||
// MCS 5bit //bit over 32, so dci_pdu ++
|
||||
pos+=5;
|
||||
@@ -882,8 +870,8 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
|
||||
// Downlink assignment index 2bit
|
||||
pos+=2;
|
||||
*dci_pdu |= ((dci_pdu_rel15->dai&3)<<(dci_size-pos));
|
||||
LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu);
|
||||
*dci_pdu |= ((dci_pdu_rel15->dai[0].val&3)<<(dci_size-pos));
|
||||
LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu);
|
||||
|
||||
// TPC command for scheduled PUCCH 2bit
|
||||
pos+=2;
|
||||
@@ -897,8 +885,8 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
|
||||
// PDSCH-to-HARQ_feedback timing indicator 3bit
|
||||
pos+=3;
|
||||
*dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_size-pos));
|
||||
LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_size-pos,*dci_pdu);
|
||||
*dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&0x7)<<(dci_size-pos));
|
||||
LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu);
|
||||
|
||||
} //end else
|
||||
break;
|
||||
@@ -914,12 +902,12 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// Freq domain assignment 0-16 bit
|
||||
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
|
||||
for (int i=0; i<fsize; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
// Time domain assignment 4 bit
|
||||
for (int i=0; i<4; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
|
||||
// VRB to PRB mapping 1 bit
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
|
||||
// MCS 5 bit
|
||||
for (int i=0; i<5; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
|
||||
@@ -935,12 +923,12 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// Freq domain assignment 0-16 bit
|
||||
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
|
||||
for (int i=0; i<fsize; i++)
|
||||
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
// Time domain assignment 4 bit
|
||||
for (int i=0; i<4; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
|
||||
// VRB to PRB mapping 1 bit
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
|
||||
// MCS 5bit //bit over 32, so dci_pdu ++
|
||||
for (int i=0; i<5; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
|
||||
@@ -956,12 +944,12 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// Freq domain assignment 0-16 bit
|
||||
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
|
||||
for (int i=0; i<fsize; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
// Time domain assignment 4 bit
|
||||
for (int i=0; i<4; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
|
||||
// VRB to PRB mapping 1 bit
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
|
||||
// MCS 5bit //bit over 32, so dci_pdu ++
|
||||
for (int i=0; i<5; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
|
||||
@@ -976,7 +964,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
|
||||
// Downlink assignment index – 2 bits
|
||||
for (int i=0; i<2; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->dai>>(1-i))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->dai[0].val>>(1-i))&1)<<(dci_size-pos++);
|
||||
|
||||
// TPC command for scheduled PUCCH – 2 bits
|
||||
for (int i=0; i<2; i++)
|
||||
@@ -989,7 +977,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
|
||||
// PDSCH-to-HARQ_feedback timing indicator – 3 bits
|
||||
for (int i=0; i<3; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val>>(2-i))&1)<<(dci_size-pos++);
|
||||
|
||||
break;
|
||||
}
|
||||
@@ -1004,12 +992,12 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// Freq domain assignment max 16 bit
|
||||
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
|
||||
for (int i=0; i<fsize; i++)
|
||||
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
// Time domain assignment 4bit
|
||||
for (int i=0; i<4; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
|
||||
// Frequency hopping flag – 1 bit
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
|
||||
// MCS 5 bit
|
||||
for (int i=0; i<5; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
|
||||
@@ -1033,7 +1021,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// UL/SUL indicator – 1 bit
|
||||
/* commented for now (RK): need to get this from BWP descriptor
|
||||
if (cfg->pucch_config.pucch_GroupHopping.value)
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
|
||||
*/
|
||||
break;
|
||||
|
||||
@@ -1044,12 +1032,12 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
// Freq domain assignment max 16 bit
|
||||
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
|
||||
for (int i=0; i<fsize; i++)
|
||||
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
|
||||
// Time domain assignment 4bit
|
||||
for (int i=0; i<4; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
|
||||
// Frequency hopping flag – 1 bit
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
|
||||
// MCS 5 bit
|
||||
for (int i=0; i<5; i++)
|
||||
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
|
||||
@@ -1074,7 +1062,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
/*
|
||||
commented for now (RK): need to get this information from BWP descriptor
|
||||
if (cfg->pucch_config.pucch_GroupHopping.value)
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
|
||||
*/
|
||||
break;
|
||||
|
||||
@@ -1084,103 +1072,73 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
case NR_DL_DCI_FORMAT_1_1:
|
||||
// Indicating a DL DCI format 1bit
|
||||
pos=1;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos);
|
||||
|
||||
// Carrier indicator
|
||||
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
|
||||
pos+=3;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator&0x7)<<(dci_size-pos);
|
||||
}
|
||||
pos+=dci_pdu_rel15->carrier_indicator.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// BWP indicator
|
||||
uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
|
||||
|
||||
nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp)));
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator&((1<<nbits)-1))<<(dci_size-pos);
|
||||
pos+=dci_pdu_rel15->bwp_indicator.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// Frequency domain resource assignment
|
||||
long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size;
|
||||
uint16_t numRBG = getNRBG(pdsch_pdu_rel15->BWPSize,pdsch_pdu_rel15->BWPStart,rbg_size_config);
|
||||
|
||||
if (pdsch_config->resourceAllocation == 0)
|
||||
nbits = numRBG;
|
||||
else if (pdsch_config->resourceAllocation == 1)
|
||||
nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
|
||||
else
|
||||
nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
|
||||
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<<nbits)-1)) << (dci_size-pos);
|
||||
pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<dci_pdu_rel15->frequency_domain_assignment.nbits)-1)) << (dci_size-pos);
|
||||
|
||||
// Time domain resource assignment
|
||||
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_timeDomList = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
|
||||
int num_entries;
|
||||
if (pdsch_timeDomList != NULL)
|
||||
num_entries = pdsch_timeDomList->list.count;
|
||||
else
|
||||
num_entries = 16; // num of entries in default table
|
||||
|
||||
nbits = (int)ceil(log2(num_entries));
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment&((1<<nbits)-1)) << (dci_size-pos);
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1)) << (dci_size-pos);
|
||||
|
||||
// VRB-to-PRB mapping
|
||||
if (pdsch_config->resourceAllocation == 1) {
|
||||
pos++;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos);
|
||||
}
|
||||
pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&((1<<dci_pdu_rel15->vrb_to_prb_mapping.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// PRB bundling size indicator
|
||||
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) {
|
||||
pos++;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator&1)<<(dci_size-pos);
|
||||
}
|
||||
pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator.val&((1<<dci_pdu_rel15->prb_bundling_size_indicator.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// Rate matching indicator
|
||||
NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1;
|
||||
NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2;
|
||||
nbits = 0;
|
||||
if ((group1 != NULL) && (group2 != NULL))
|
||||
nbits = 2;
|
||||
if ((group1 != NULL) != (group2 != NULL))
|
||||
nbits = 1;
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator&((1<<nbits)-1))<<(dci_size-pos);
|
||||
|
||||
pos+=dci_pdu_rel15->rate_matching_indicator.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator.val&((1<<dci_pdu_rel15->rate_matching_indicator.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// ZP CSI-RS trigger
|
||||
uint8_t nZP = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count;
|
||||
nbits = (int)ceil(log2(nZP+1));
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger&((1<<nbits)-1)) << (dci_size-pos);
|
||||
pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger.val&((1<<dci_pdu_rel15->zp_csi_rs_trigger.nbits)-1)) << (dci_size-pos);
|
||||
|
||||
//TB1
|
||||
// MCS 5bit
|
||||
pos+=5;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
|
||||
|
||||
// New data indicator 1bit
|
||||
pos++;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos);
|
||||
pos+=1;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos);
|
||||
|
||||
// Redundancy version 2bit
|
||||
pos+=2;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos);
|
||||
|
||||
//TB2
|
||||
// MCS 5bit
|
||||
pos+=dci_pdu_rel15->mcs2.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs2.val&((1<<dci_pdu_rel15->mcs2.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// New data indicator 1bit
|
||||
pos+=dci_pdu_rel15->ndi2.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi2.val&((1<<dci_pdu_rel15->ndi2.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// Redundancy version 2bit
|
||||
pos+=dci_pdu_rel15->rv2.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv2.val&((1<<dci_pdu_rel15->rv2.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// HARQ process number 4bit
|
||||
pos+=4;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos);
|
||||
|
||||
// Downlink assignment index
|
||||
if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells
|
||||
pos+=4;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0xf)<<(dci_size-pos);
|
||||
}
|
||||
/* else if (0) {
|
||||
pos+=2;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0x3)<<(dci_size-pos);
|
||||
}
|
||||
*/
|
||||
pos+=dci_pdu_rel15->dai[0].nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<<dci_pdu_rel15->dai[0].nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// TPC command for scheduled PUCCH 2bit
|
||||
pos+=2;
|
||||
@@ -1191,46 +1149,28 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos);
|
||||
|
||||
// PDSCH-to-HARQ_feedback timing indicator
|
||||
uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count;
|
||||
nbits = (int)ceil(log2(I));
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&((1<<nbits)-1))<<(dci_size-pos);
|
||||
pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&((1<<dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// Antenna ports
|
||||
NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA;
|
||||
NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB;
|
||||
nbits = getAntPortBitWidth(typeA,typeB);
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports&((1<<nbits)-1))<<(dci_size-pos);
|
||||
pos+=dci_pdu_rel15->antenna_ports.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<<dci_pdu_rel15->antenna_ports.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// TCI
|
||||
long *isTciEnable = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI;
|
||||
if (isTciEnable != NULL) {
|
||||
pos+=3;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication&0x7)<<(dci_size-pos);
|
||||
}
|
||||
pos+=dci_pdu_rel15->transmission_configuration_indication.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication.val&((1<<dci_pdu_rel15->transmission_configuration_indication.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// SRS request
|
||||
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL)
|
||||
nbits = 2;
|
||||
else
|
||||
nbits = 3;
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request&((1<<nbits)-1))<<(dci_size-pos);
|
||||
pos+=dci_pdu_rel15->srs_request.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<<dci_pdu_rel15->srs_request.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// CBG transmission information
|
||||
uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_ServingCellConfig->choise.setup->codeBlockGroupTransmission->choise.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2;
|
||||
long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI;
|
||||
uint8_t maxCWperDCI = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc;
|
||||
nbits = maxCBGperTB * maxCWperDCI;
|
||||
pos+=nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti&((1<<nbits)-1))<<(dci_size-pos);
|
||||
pos+=dci_pdu_rel15->cbgti.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<<dci_pdu_rel15->cbgti.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// CBG flushing out information
|
||||
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_ServingCellConfig->choise.setup->codeBlockGroupTransmission->choise.setup->codeBlockGroupFlushIndicator) {
|
||||
pos+=1;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi&0x1)<<(dci_size-pos);
|
||||
}
|
||||
pos+=dci_pdu_rel15->cbgfi.nbits;
|
||||
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<<dci_pdu_rel15->cbgfi.nbits)-1))<<(dci_size-pos);
|
||||
|
||||
// DMRS sequence init
|
||||
pos+=1;
|
||||
|
||||
@@ -148,9 +148,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
|
||||
NR_BWP_Downlink_t *bwp);
|
||||
|
||||
void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15,
|
||||
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
|
||||
nfapi_nr_pusch_pdu_t *pusch_pdu,
|
||||
dci_pdu_rel15_t *dci_pdu_rel15,
|
||||
int *dci_formats,
|
||||
int *rnti_types);
|
||||
@@ -192,9 +190,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP);
|
||||
|
||||
int get_num_dmrs(uint16_t dmrs_mask );
|
||||
|
||||
uint16_t nr_dci_size(nr_dci_format_t format,
|
||||
nr_rnti_type_t rnti_type,
|
||||
uint16_t N_RB);
|
||||
uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
dci_pdu_rel15_t *dci_pdu,
|
||||
nr_dci_format_t format,
|
||||
nr_rnti_type_t rnti_type,
|
||||
uint16_t N_RB);
|
||||
|
||||
int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
|
||||
int bwp_id,
|
||||
|
||||
@@ -203,7 +203,7 @@ typedef struct gNB_MAC_INST_s {
|
||||
int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
|
||||
} gNB_MAC_INST;
|
||||
|
||||
typedef struct {
|
||||
/*typedef struct {
|
||||
|
||||
|
||||
uint8_t format_indicator; //1 bit
|
||||
@@ -263,8 +263,71 @@ uint8_t antenna_ports;
|
||||
uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
|
||||
uint16_t padding;
|
||||
|
||||
} dci_pdu_rel15_t;*/
|
||||
|
||||
typedef struct {
|
||||
uint16_t val;
|
||||
uint8_t nbits;
|
||||
} dci_field_t;
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
uint8_t format_indicator; //1 bit
|
||||
uint8_t ra_preamble_index; //6 bits
|
||||
uint8_t ss_pbch_index; //6 bits
|
||||
uint8_t prach_mask_index; //4 bits
|
||||
uint8_t mcs; //5 bits
|
||||
uint8_t ndi; //1 bit
|
||||
uint8_t rv; //2 bits
|
||||
uint8_t harq_pid; //4 bits
|
||||
uint8_t tpc; //2 bits
|
||||
uint8_t short_messages_indicator; //2 bits
|
||||
uint8_t short_messages; //8 bits
|
||||
uint8_t tb_scaling; //2 bits
|
||||
uint8_t pucch_resource_indicator; //3 bits
|
||||
uint8_t dmrs_sequence_initialization; //1 bit
|
||||
uint8_t system_info_indicator; //1 bit
|
||||
|
||||
uint8_t slot_format_indicator_count;
|
||||
uint8_t *slot_format_indicators;
|
||||
|
||||
uint8_t pre_emption_indication_count;
|
||||
uint16_t *pre_emption_indications; //14 bit each
|
||||
|
||||
uint8_t block_number_count;
|
||||
uint8_t *block_numbers;
|
||||
uint8_t padding;
|
||||
|
||||
dci_field_t mcs2; //variable
|
||||
dci_field_t ndi2; //variable
|
||||
dci_field_t rv2; //variable
|
||||
dci_field_t frequency_domain_assignment; //variable
|
||||
dci_field_t time_domain_assignment; //variable
|
||||
dci_field_t frequency_hopping_flag; //variable
|
||||
dci_field_t vrb_to_prb_mapping; //variable
|
||||
dci_field_t dai[2]; //variable
|
||||
dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable
|
||||
dci_field_t carrier_indicator; //variable
|
||||
dci_field_t bwp_indicator; //variable
|
||||
dci_field_t prb_bundling_size_indicator; //variable
|
||||
dci_field_t rate_matching_indicator; //variable
|
||||
dci_field_t zp_csi_rs_trigger; //variable
|
||||
dci_field_t transmission_configuration_indication; //variable
|
||||
dci_field_t srs_request; //variable
|
||||
dci_field_t cbgti; //variable
|
||||
dci_field_t cbgfi; //variable
|
||||
dci_field_t srs_resource_indicator; //variable
|
||||
dci_field_t precoding_information; //variable
|
||||
dci_field_t csi_request; //variable
|
||||
dci_field_t ptrs_dmrs_association; //variable
|
||||
dci_field_t beta_offset_indicator; //variable
|
||||
dci_field_t cloded_loop_indicator; //variable
|
||||
dci_field_t ul_sul_indicator; //variable
|
||||
dci_field_t antenna_ports; //variable
|
||||
dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
|
||||
|
||||
} dci_pdu_rel15_t;
|
||||
|
||||
|
||||
|
||||
#endif /*__LAYER2_NR_MAC_GNB_H__ */
|
||||
|
||||
Reference in New Issue
Block a user