Fix for dlsch issue on caracal
1. Reducing rx gain at UE. Existing gain seems to saturate the receiver with full bw allocaiton. 2. Setting different dlsch bitmap for phytest mode.
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@@ -52,7 +52,7 @@
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<testCase id="090102">
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<class>Initialize_OAI_UE</class>
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<desc>Initialize NR UE USRP</desc>
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<Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 75 --rrc_config_path .</Initialize_OAI_UE_args>
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<Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 50 --rrc_config_path .</Initialize_OAI_UE_args>
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<air_interface>NR</air_interface>
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</testCase>
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@@ -360,9 +360,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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nr_rrc_trigger(&ctxt, 0 /*CC_id*/, frame, slot >> *scc->ssbSubcarrierSpacing);
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}
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const uint64_t dlsch_in_slot_bitmap = (1 << 1) | (1 << 3);
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uint64_t dlsch_in_slot_bitmap = (1 << 1) | (1 << 3);
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const uint64_t ulsch_in_slot_bitmap = (1 << 8);
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if (get_softmodem_params()->phy_test) // for testing with OAI-UE
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dlsch_in_slot_bitmap = (1 << 1);
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memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
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memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
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for (int i=0; i<MAX_NUM_CORESET; i++)
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