removing bwp from pdcch_pdu_idx and cce_list
This commit is contained in:
@@ -1038,8 +1038,8 @@ int main(int argc, char **argv)
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while ((round<num_rounds) && (UE_harq_process->ack==0)) {
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memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int));
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memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int));
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memset(RC.nrmac[0]->cce_list[0],0,MAX_NUM_CCE*sizeof(int));
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memset(RC.nrmac[0]->cce_list[1],0,MAX_NUM_CCE*sizeof(int));
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clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
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UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].ndi = !(trial&1);
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@@ -67,7 +67,7 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
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const int num_slots = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
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nfapi_nr_dl_tti_request_t *DL_req = &gNB->DL_req[0];
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t ***pdcch = (nfapi_nr_dl_tti_pdcch_pdu_rel15_t ***)gNB->pdcch_pdu_idx[CC_idP];
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t **pdcch = (nfapi_nr_dl_tti_pdcch_pdu_rel15_t **)gNB->pdcch_pdu_idx[CC_idP];
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nfapi_nr_ul_tti_request_t *future_ul_tti_req =
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&gNB->UL_tti_req_ahead[CC_idP][(slotP + num_slots - 1) % num_slots];
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nfapi_nr_ul_dci_request_t *UL_dci_req = &gNB->UL_dci_req[0];
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@@ -80,7 +80,7 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
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DL_req[CC_idP].dl_tti_request_body.nPDUs = 0;
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DL_req[CC_idP].dl_tti_request_body.nGroup = 0;
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//DL_req[CC_idP].dl_tti_request_body.transmission_power_pcfich = 6000;
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memset(pdcch, 0, sizeof(**pdcch) * MAX_NUM_BWP * MAX_NUM_CORESET);
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memset(pdcch, 0, sizeof(*pdcch) * MAX_NUM_CORESET);
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UL_dci_req[CC_idP].SFN = frameP;
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UL_dci_req[CC_idP].Slot = slotP;
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@@ -276,7 +276,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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protocol_ctxt_t ctxt={0};
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PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame, slot,module_idP);
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const int bwp_id = 1;
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char stats_output[16384];
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gNB_MAC_INST *gNB = RC.nrmac[module_idP];
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@@ -307,9 +306,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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nr_rrc_trigger(&ctxt, 0 /*CC_id*/, frame, slot >> *scc->ssbSubcarrierSpacing);
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}
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memset(RC.nrmac[module_idP]->cce_list[0][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
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memset(RC.nrmac[module_idP]->cce_list[0][1],0,MAX_NUM_CCE*sizeof(int)); // coreset1 on initialBWP
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memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
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memset(RC.nrmac[module_idP]->cce_list[0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
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memset(RC.nrmac[module_idP]->cce_list[1],0,MAX_NUM_CCE*sizeof(int)); // coreset1
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NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info;
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for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id])
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for (int i=0; i<MAX_NUM_CORESET; i++)
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@@ -780,7 +780,7 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
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nfapi_nr_ul_dci_request_t *ul_dci_req = &nr_mac->UL_dci_req[CC_id];
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const int coresetid = coreset->controlResourceSetId;
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id][coresetid];
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
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if (!pdcch_pdu_rel15) {
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nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
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memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
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@@ -789,7 +789,7 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
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pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
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ul_dci_req->numPdus += 1;
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nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, ss, coreset, scc, genericParameters, NULL);
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nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id][coresetid] = pdcch_pdu_rel15;
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nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu_rel15;
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}
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uint8_t aggregation_level;
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@@ -1196,7 +1196,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
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const int bwpid = bwp ? bwp->bwp_Id : 0;
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const int coresetid = coreset->controlResourceSetId;
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid];
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
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if (!pdcch_pdu_rel15) {
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
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@@ -1205,7 +1205,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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dl_req->nPDUs += 1;
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pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
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nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, ss, coreset, scc, genericParameters, NULL);
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nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu_rel15;
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nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu_rel15;
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}
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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@@ -1572,7 +1572,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
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const int bwpid = bwp ? bwp->bwp_Id : 0;
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const int coresetid = coreset->controlResourceSetId;
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid];
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
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if (!pdcch_pdu_rel15) {
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
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@@ -1581,7 +1581,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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dl_req->nPDUs += 1;
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pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
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nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, ss, coreset, scc, genericParameters, NULL);
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nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu_rel15;
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nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu_rel15;
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}
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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@@ -627,7 +627,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
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slot);
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int cid = sched_ctrl->coreset->controlResourceSetId;
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UE_info->num_pdcch_cand[UE_id][cid]--;
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int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp?sched_ctrl->active_bwp->bwp_Id:0][cid];
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int *cce_list = RC.nrmac[module_id]->cce_list[cid];
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for (int i = 0; i < sched_ctrl->aggregation_level; i++)
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cce_list[sched_ctrl->cce_index + i] = 0;
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return false;
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@@ -732,7 +732,6 @@ void pf_dl(module_id_t module_id,
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NR_BWP_DownlinkDedicated_t *bwpd= cg ? cg->spCellConfig->spCellConfigDedicated->initialDownlinkBWP:NULL;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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int bwp_Id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0;
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const uint16_t rnti = UE_info->rnti[UE_id];
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NR_BWP_t *genericParameters = sched_ctrl->active_bwp ?
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&sched_ctrl->active_bwp->bwp_Common->genericParameters:
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@@ -764,7 +763,7 @@ void pf_dl(module_id_t module_id,
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slot);
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int cid = sched_ctrl->coreset->controlResourceSetId;
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UE_info->num_pdcch_cand[UE_id][cid]--;
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int *cce_list = mac->cce_list[bwp_Id][cid];
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int *cce_list = mac->cce_list[cid];
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for (int i = 0; i < sched_ctrl->aggregation_level; i++)
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cce_list[sched_ctrl->cce_index + i] = 0;
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return;
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@@ -995,7 +994,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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const int bwpid = bwp ? bwp->bwp_Id : 0;
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const int coresetid = (bwp||bwpd) ? sched_ctrl->coreset->controlResourceSetId : gNB_mac->sched_ctrlCommon->coreset->controlResourceSetId;
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = gNB_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid];
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = gNB_mac->pdcch_pdu_idx[CC_id][coresetid];
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if (!pdcch_pdu) {
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
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@@ -1007,7 +1006,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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NR_SearchSpace_t *ss = (bwp||bwpd) ? sched_ctrl->search_space:gNB_mac->sched_ctrlCommon->search_space;
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NR_ControlResourceSet_t *coreset = (bwp||bwpd)? sched_ctrl->coreset:gNB_mac->sched_ctrlCommon->coreset;
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nr_configure_pdcch(gNB_mac, pdcch_pdu, ss, coreset, scc, genericParameters, NULL);
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gNB_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu;
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gNB_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu;
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}
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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@@ -358,7 +358,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
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frame,
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slot);
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UE_info->num_pdcch_cand[UE_id][cid]--;
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int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp->bwp_Id][cid];
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int *cce_list = RC.nrmac[module_id]->cce_list[cid];
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for (int i = 0; i < sched_ctrl->aggregation_level; i++)
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cce_list[sched_ctrl->cce_index + i] = 0;
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return;
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@@ -218,12 +218,7 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
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int coreset_id = coreset->controlResourceSetId;
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int *cce_list;
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if(bwp == NULL) {
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cce_list = nr_mac->cce_list[0][coreset_id];
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} else {
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cce_list = nr_mac->cce_list[bwp->bwp_Id][coreset_id];
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}
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int *cce_list = nr_mac->cce_list[coreset_id];
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int n_rb=0;
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for (int i=0;i<6;i++)
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@@ -2410,7 +2405,7 @@ bool find_free_CCE(module_id_t module_id,
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const int cid = sched_ctrl->coreset->controlResourceSetId;
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const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid][slot];
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const int m = RC.nrmac[module_id]->UE_info.num_pdcch_cand[UE_id][cid];
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if (UE_id >= 0) LOG_D(NR_MAC,"calling allocate_nr_CCEs with L %d, nr_of_candidates %d, Y %x\n",sched_ctrl->aggregation_level,nr_of_candidates,Y);
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if (UE_id >= 0) LOG_D(NR_MAC,"slot %d calling allocate_nr_CCEs with L %d, nr_of_candidates %d, Y %x\n",slot, sched_ctrl->aggregation_level,nr_of_candidates,Y);
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sched_ctrl->cce_index = allocate_nr_CCEs(RC.nrmac[module_id],
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sched_ctrl->active_bwp,
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sched_ctrl->coreset,
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@@ -1388,10 +1388,6 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
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nfapi_nr_ul_dci_request_t *ul_dci_req = &RC.nrmac[module_id]->UL_dci_req[CC_id];
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ul_dci_req->SFN = frame;
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ul_dci_req->Slot = slot;
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/* a PDCCH PDU groups DCIs per BWP and CORESET. Save a pointer to each
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* allocated PDCCH so we can easily allocate UE's DCIs independent of any
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* CORESET order */
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_bwp_coreset[MAX_NUM_BWP][MAX_NUM_CORESET] = {{0}};
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NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
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NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
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@@ -1628,7 +1624,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
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NR_SearchSpace_t *ss = (sched_ctrl->active_bwp || ubwpd) ? sched_ctrl->search_space: RC.nrmac[module_id]->sched_ctrlCommon->search_space;
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NR_ControlResourceSet_t *coreset = (sched_ctrl->active_bwp || ubwpd) ? sched_ctrl->coreset: RC.nrmac[module_id]->sched_ctrlCommon->coreset;
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const int coresetid = coreset->controlResourceSetId;
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = pdcch_pdu_bwp_coreset[bwpid][coresetid];
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
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if (!pdcch_pdu) {
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nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
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memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
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@@ -1637,7 +1633,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
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pdcch_pdu = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
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ul_dci_req->numPdus += 1;
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nr_configure_pdcch(nr_mac, pdcch_pdu, ss, coreset, scc, genericParameters, NULL);
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pdcch_pdu_bwp_coreset[bwpid][coresetid] = pdcch_pdu;
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nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu;
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}
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LOG_D(NR_MAC,"Configuring ULDCI/PDCCH in %d.%d at CCE %d, rnti %x\n", frame,slot,sched_ctrl->cce_index,rnti);
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@@ -73,7 +73,7 @@
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/* Defs */
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#define MAX_NUM_BWP 2
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#define MAX_NUM_CORESET 2
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#define MAX_NUM_CORESET 12
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#define MAX_NUM_CCE 90
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#define MAX_HARQ_ROUNDS 4
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/*!\brief Maximum number of random access process */
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@@ -703,7 +703,7 @@ typedef struct gNB_MAC_INST_s {
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/// a PDCCH PDU groups DCIs per BWP and CORESET. The following structure
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/// keeps pointers to PDCCH PDUs within DL_req so that we can easily track
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/// PDCCH PDUs per CC/BWP/CORESET
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_idx[NFAPI_CC_MAX][MAX_NUM_BWP][MAX_NUM_CORESET];
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_idx[NFAPI_CC_MAX][MAX_NUM_CORESET];
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/// NFAPI UL TTI Request Structure, simple pointer into structure
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/// UL_tti_req_ahead for current frame/slot
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nfapi_nr_ul_tti_request_t *UL_tti_req[NFAPI_CC_MAX];
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@@ -743,7 +743,7 @@ typedef struct gNB_MAC_INST_s {
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/// processing time of eNB PCH scheduler
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time_stats_t schedule_pch;
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/// CCE lists
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int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
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int cce_list[MAX_NUM_CORESET][MAX_NUM_CCE];
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/// list of allocated beams per period
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int16_t *tdd_beam_association;
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