Ensure execution of processSlotTX in order in NR UE
Make sure that processSlotTX is executed in slot order.
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+13
-1
@@ -569,6 +569,7 @@ void processSlotTX(void *arg)
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}
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}
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RU_write(rxtxD, sl_tx_action);
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dynamic_barrier_join(rxtxD->next_barrier);
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TracyCZoneEnd(ctx);
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}
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@@ -1111,8 +1112,19 @@ void *UE_thread(void *arg)
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int slot = curMsgTx->proc.nr_slot_tx;
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int slot_and_frame = slot + curMsgTx->proc.frame_tx * UE->frame_parms.slots_per_frame;
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int wait_for_prev_slot = stream_status == STREAM_STATUS_SYNCED ? 1 : 0;
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int next_duration_rx_to_tx =
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update_ntn_system_information
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? NR_UE_CAPABILITY_SLOT_RX_TO_TX + UE->ntn_config_message->ntn_config_params.cell_specific_k_offset
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: duration_rx_to_tx;
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int next_nr_slot_tx = (absolute_slot + next_duration_rx_to_tx) % nb_slot_frame;
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int next_frame_tx = ((absolute_slot + next_duration_rx_to_tx) / nb_slot_frame) % MAX_FRAME_NUMBER;
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int next_tx_slot_and_frame = next_nr_slot_tx + next_frame_tx * UE->frame_parms.slots_per_frame + 1;
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dynamic_barrier_t *next_barrier = &UE->process_slot_tx_barriers[next_tx_slot_and_frame % NUM_PROCESS_SLOT_TX_BARRIERS];
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curMsgTx->next_barrier = next_barrier;
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dynamic_barrier_update(&UE->process_slot_tx_barriers[slot_and_frame % NUM_PROCESS_SLOT_TX_BARRIERS],
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tx_wait_for_dlsch[slot],
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tx_wait_for_dlsch[slot] + wait_for_prev_slot,
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start_process_slot_tx,
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newTx);
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stream_status = STREAM_STATUS_SYNCED;
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@@ -627,6 +627,7 @@ typedef struct nr_rxtx_thread_data_s {
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PHY_VARS_NR_UE *UE;
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int writeBlockSize;
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nr_phy_data_t phy_data;
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dynamic_barrier_t *next_barrier;
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} nr_rxtx_thread_data_t;
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typedef struct LDPCDecode_ue_s {
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