changed name of function initial pdcch scheduling parameters. Currently we set the BWP information to be the full bandwidth of the NR cell. This should be changed to include the CellGroupConfigCommon initial BWP information either from SIB or from LTE RRC.

DCI still not updated to start from MSB. Will be in next commit
This commit is contained in:
Raymond Knopp
2018-12-03 12:25:55 +01:00
parent d31bf6f962
commit e7c63993d6
7 changed files with 36 additions and 34 deletions
@@ -1149,7 +1149,7 @@ uint32_t polar_decoder_int16(int16_t *input,
crc = (uint64_t)(crc24c(A64_flip,len)>>8);
}
#if 0
#if 1
printf("A %llx B %llx|%llx Cprime %llx|%llx (crc %x,rxcrc %llx %d)\n",
Ar,
B[1],B[0],Cprime[1],Cprime[0],crc,
@@ -30,7 +30,7 @@
* \warning
*/
//#define DEBUG_POLAR_ENCODER
#define DEBUG_POLAR_ENCODER
//#define DEBUG_POLAR_ENCODER_DCI
//#define DEBUG_POLAR_ENCODER_TIMING
@@ -391,7 +391,8 @@ void polar_encoder_fast(uint64_t *A,
t_nrPolar_paramsPtr polarParams) {
AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K);
AssertFatal(polarParams->K < 129, "K = %d > 64, is not supported yet\n",polarParams->K);
AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K);
AssertFatal(polarParams->payloadBits < 65, "payload bits = %d > 64, is not supported yet\n",polarParams->payloadBits);
uint64_t B[4]={0,0,0,0},Cprime[4]={0,0,0,0};
int bitlen = polarParams->payloadBits;
+3 -3
View File
@@ -32,9 +32,9 @@
#include "nr_dci.h"
//#define DEBUG_PDCCH_DMRS
//#define DEBUG_DCI
//#define DEBUG_CHANNEL_CODING
#define DEBUG_PDCCH_DMRS
#define DEBUG_DCI
#define DEBUG_CHANNEL_CODING
#define PDCCH_TEST_POLAR_TEMP_FIX
extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT];
+6 -5
View File
@@ -112,15 +112,16 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
NR_gNB_DCI_ALLOC_t *dci_alloc,
nfapi_nr_dl_config_request_pdu_t *pdu)
{
NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
uint8_t n_shift;
uint32_t *dci_pdu = dci_alloc->dci_pdu;
uint32_t *dci_pdu = dci_alloc->dci_pdu;
memset((void*)dci_pdu,0,4*sizeof(uint32_t));
nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &pdu->dci_dl_pdu.dci_dl_pdu_rel15;
nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &pdu->dci_dl_pdu.dci_dl_pdu_rel15;
nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &pdu->dci_dl_pdu.pdcch_params_rel15;
nfapi_nr_config_request_t *cfg = &gNB->gNB_config;
uint16_t N_RB = fp->initial_bwp_dl.N_RB;
nfapi_nr_config_request_t *cfg = &gNB->gNB_config;
uint16_t N_RB = params_rel15->n_RB_BWP;
uint8_t fsize=0, pos=0, cand_idx=0;
/// Payload generation
@@ -59,8 +59,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
LOG_I(MAC, "Scheduling common search space DCI type 1 for CC_id %d\n",CC_id);
dl_req = &nr_mac->DL_req[CC_id].dl_config_request_body;
dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu];
memset((void*)dl_config_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t));
@@ -70,11 +68,11 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel15;
nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &dl_config_pdu->dci_dl_pdu.pdcch_params_rel15;
nr_configure_css_dci_from_mib(params_rel15,
scs, scs, nr_FR1, 0, 0,
slots_per_frame,
dl_carrier_bandwidth);
nr_configure_css_dci_initial(params_rel15,
scs, scs, nr_FR1, 0, 0,
slots_per_frame,
dl_carrier_bandwidth);
pdu_rel15->frequency_domain_assignment = 5;
pdu_rel15->time_domain_assignment = 2;
pdu_rel15->vrb_to_prb_mapping = 0;
@@ -140,14 +140,14 @@ int is_nr_UL_sf(NR_COMMON_channels_t * ccP, sub_frame_t subframeP){
}
}
void nr_configure_css_dci_from_mib(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nr_scs_e scs_common,
nr_scs_e pdcch_scs,
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint16_t nb_slots_per_frame,
uint16_t N_RB)
void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nr_scs_e scs_common,
nr_scs_e pdcch_scs,
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint16_t nb_slots_per_frame,
uint16_t N_RB)
{
uint8_t O, M;
uint8_t ss_idx = rmsi_pdcch_config&0xf;
@@ -250,6 +250,8 @@ void nr_configure_css_dci_from_mib(nfapi_nr_dl_config_pdcch_parameters_rel15_t*
pdcch_params->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE;
pdcch_params->reg_bundle_size = 6;
pdcch_params->interleaver_size = 2;
// set initial banwidth part to full bandwidth
pdcch_params->n_RB_BWP = N_RB;
}
void nr_configure_css_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
+8 -8
View File
@@ -66,14 +66,14 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
sub_frame_t subframeP);
void nr_configure_css_dci_from_mib(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nr_scs_e scs_common,
nr_scs_e pdcch_scs,
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint16_t nb_slots_per_frame,
uint16_t N_RB);
void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nr_scs_e scs_common,
nr_scs_e pdcch_scs,
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint16_t nb_slots_per_frame,
uint16_t N_RB);
void nr_configure_css_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,