added some fields in 1_1 DCI bit encoder
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@@ -387,7 +387,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
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rnti_types[0] = NR_RNTI_C;
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pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
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fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
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fill_dci_pdu_rel15(pdsch_pdu_rel_15,NULL,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
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LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
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coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
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@@ -833,7 +833,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
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config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
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pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
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fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
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fill_dci_pdu_rel15(NULL,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
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}
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@@ -546,7 +546,9 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
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void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15,
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nfapi_nr_pusch_pdu_t *pusch_pdu,
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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dci_pdu_rel15_t *dci_pdu_rel15,
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int *dci_formats,
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int *rnti_types
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@@ -554,6 +556,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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uint16_t N_RB = pdcch_pdu_rel15->BWPSize;
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uint8_t fsize=0, pos=0;
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uint8_t nbits=0;
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for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
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@@ -561,6 +564,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
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int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d];
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pos = 0;
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/// Payload generation
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switch(dci_formats[d]) {
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@@ -864,6 +868,110 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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}
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break;
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case NR_DL_DCI_FORMAT_1_1:
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// Indicating a DL DCI format 1bit
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pos=1;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos);
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// Carrier indicator
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if (!dci_pdu_rel15->carrier_indicator) {// TODO: check if UE configured with CrossCarrierSchedulingConfig
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pos+=3;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator&0x7)<<(dci_size-pos);
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}
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// BWP indicator
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uint8_t n_bwp_rrc = 0; // TODO: get this parameter from RRC
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nbits = (uint8_t)((n_bwp_rrc < 4) ? ceil(log2(n_bwp_rrc+1)) : ceil(log2(n_bwp_rrc)));
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pos+=nbits;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator&((1<<nbits)-1)<<(dci_size-pos);
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// Frequency domain resource assignment
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uint16_t numRBG = 0; // TODO: replace with N_RBG (couldn't find it)
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if (pdsch_pdu_rel15->resourceAlloc == 0)
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nbits = numRBG;
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else if (pdsch_pdu_rel15->resourceAlloc == 1)
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nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
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else
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nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
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pos+=nbits;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<<nbits)-1)) << (dci_size-pos);
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// Time domain resource assignment
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uint8_t num_entries;
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if (0) // TODO: check if pdschTimeDomainAllocationList exists
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num_entries = 0; // TODO: replace with number of entries in pdschTimeDomainAllocationList
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else
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num_entries = 16;
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nbits = (int)ceil(log2(num_entries));
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pos+=nbits;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment&((1<<nbits)-1)) << (dci_size-pos);
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// VRB-to-PRB mapping
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if (pdsch_pdu_rel15->resourceAlloc == 1) {
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pos++;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos);
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}
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// PRB bundling size indicator
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if (0) {// TODO: check if prb-BundlingType is dynamic
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pos++;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator&1)<<(dci_size-pos);
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}
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// Rate matching indicator
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// TODO: check for rateMatchPatternGroup
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// ZP CSI-RS trigger
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uint8_t nZP = 0; // TODO: replace with number of aperiodic ZP CSI-RS resource sets
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nbits = (int)ceil(log2(nZP+1));
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pos+=nbits;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger&((1<<nbits)-1)) << (dci_size-pos);
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// MCS 5bit
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pos+=5;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
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// New data indicator 1bit
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pos++;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos);
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// Redundancy version 2bit
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pos+=2;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos);
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// HARQ process number 4bit
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pos+=4;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos);
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// Downlink assignment index
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if (0) { // TODO: check if UE has more than 1 serving cell AND pdsch-HARQ-ACK-Codebook is dynamic
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pos+=4;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0xf)<<(dci_size-pos);
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} else if (0) { // TODO: check if UE had only 1 serving cell AND "
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pos+=2;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0x3)<<(dci_size-pos);
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}
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// TPC command for scheduled PUCCH 2bit
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pos+=2;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos);
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// PUCCH resource indicator 3bit
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pos+=3;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos);
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// PDSCH-to-HARQ_feedback timing indicator
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uint8_t I = 0; // TODO: replace with number of entries in dl-DataToUL-ACK
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nbits = (int)ceil(log2(I));
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pos+=nbits;
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*dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&((1<<nbits)-1))<<(dci_size-pos);
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}
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}
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}
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@@ -130,7 +130,9 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
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NR_ServingCellConfigCommon_t *scc,
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NR_BWP_Downlink_t *bwp);
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void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15,
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nfapi_nr_pusch_pdu_t *pusch_pdu,
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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dci_pdu_rel15_t *dci_pdu_rel15,
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int *dci_formats,
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int *rnti_types);
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