Use vrb_map in in DL for NSA mode
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@@ -444,8 +444,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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//mbsfn_status[CC_id] = 0;
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// clear vrb_maps
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memset(cc[CC_id].vrb_map, 0, 100);
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memset(cc[CC_id].vrb_map_UL, 0, 100);
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memset(cc[CC_id].vrb_map, 0, 275);
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memset(cc[CC_id].vrb_map_UL, 0, 275);
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clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame, slot);
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}
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@@ -550,7 +550,6 @@ void nr_generate_Msg2(module_id_t module_idP,
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uint16_t RA_rnti = ra->RA_rnti;
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long locationAndBandwidth;
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// uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id;
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// check if UE is doing RA on CORESET0 , InitialBWP or configured BWP from SCD
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// get the BW of the PDCCH for PDCCH size and RAR PDSCH size
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@@ -740,6 +739,11 @@ void nr_generate_Msg2(module_id_t module_idP,
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nr_mac->TX_req[CC_id].Number_of_PDUs++;
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nr_mac->TX_req[CC_id].Slot = slotP;
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memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length);
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/* mark the corresponding RBs as used */
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uint8_t *vrb_map = cc[CC_id].vrb_map;
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for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++)
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vrb_map[rb + pdsch_pdu_rel15->rbStart] = 1;
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}
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}
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@@ -137,6 +137,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){
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dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag = 1;
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dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload = (*(uint32_t*)cc->MIB_pdu.payload) & ((1<<24)-1);
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dl_req->nPDUs++;
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uint8_t *vrb_map = cc[CC_id].vrb_map;
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const int rbStart = dl_config_pdu->ssb_pdu.ssb_pdu_rel15.ssbOffsetPointA;
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for (int rb = 0; rb < 20; rb++)
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vrb_map[rbStart + rb] = 1;
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}
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}
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}
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@@ -517,9 +517,19 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
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sched_ctrl->time_domain_allocation = 2;
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// Freq-demain allocation
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uint8_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
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const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
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sched_ctrl->rbSize = bwpSize;
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sched_ctrl->rbStart = 0;
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int rbStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
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while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
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int rbSize = 1;
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while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize]) rbSize++;
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DevAssert(rbSize >= 3); /* just ensure we have at least 3 RBs */
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sched_ctrl->rbSize = rbSize;
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sched_ctrl->rbStart = rbStart;
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/* mark the corresponding RBs as used */
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for (int rb = 0; rb < sched_ctrl->rbSize; rb++)
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vrb_map[rb + sched_ctrl->rbStart] = 1;
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// modulation scheme
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sched_ctrl->mcsTableIdx = 0;
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@@ -172,9 +172,9 @@ typedef struct {
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/// Template for RA computations
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NR_RA_t ra[NR_NB_RA_PROC_MAX];
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/// VRB map for common channels
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uint8_t vrb_map[100];
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uint8_t vrb_map[275];
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/// VRB map for common channels and retransmissions by PHICH
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uint8_t vrb_map_UL[100];
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uint8_t vrb_map_UL[275];
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/// number of subframe allocation pattern available for MBSFN sync area
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uint8_t num_sf_allocation_pattern;
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} NR_COMMON_channels_t;
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