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1505 Commits
Author SHA1 Message Date
Cedric Roux 8dd8a97c34 compilation warning removal 2017-03-24 11:55:32 +01:00
Cedric Roux 11856c6b00 compilation warning removal: allocate_REs set but not used 
I removed this variable entirely because it's not used.

Maybe the bug is that it's not used after being set?
To be checked and fixed at some point.
 2017-03-24 11:53:34 +01:00
Cedric Roux 774452bbbb compilation warning removal 
this variable does not seem to be used, to be removed?
 2017-03-24 11:50:56 +01:00
Cedric Roux 4fcb6272f4 RRC Rel14 
- import RRC ASN.1 defintions from the specifications
  (file openair2/RRC/LITE/MESSAGES/asn1c/ASN1_files/RRC-e10.asn)
  contrary to rel8/10, all modules have been imported, maybe it's too much
  to refine in case of problems
- deal with rel14 in fix_asn1
- all code that was for Rel10 is now for Rel10/Rel14
- some incompatible changes (mostly in naming) were resolved in favor
  of rel14, see in openair2/RRC/LITE/defs.h
- unsure about the rlc layer, some arrays have changed (values appended),
  I only changed the definition and in tests in the code, I changed
  the index limit, maybe it's not enough

Rel14 is the default compilation mode.
 2017-03-23 18:06:40 +01:00
Elena_Lukashova b88fec2304 Some more printouts for rank adaptation. 2017-03-21 23:15:24 +01:00
Elena_Lukashova 23109e1a82 Optimizing bler files for rank adaptation. 2017-03-21 21:06:25 +01:00
Elena_Lukashova 9d2a4717d0 Changing the bler computation and printouts for the rank adaptation in tm4. 
Now it counts how many times the TBs were set to active.
 2017-03-21 18:52:41 +01:00
Elena_Lukashova 6219ddc581 Rank adaptation is now an argument of the command line. 2017-03-21 15:17:42 +01:00
Calisson 9d3eed3b43 fixing ulsim 2017-03-21 15:02:20 +01:00
Elena_Lukashova 48d7a1ef3a Fixing arguments of lte_ue_measurements in pbchsim.c 2017-03-21 14:35:32 +01:00
Calisson 7685cf1811 fixing srs in msg3. now all SRS subframe configs work. 2017-03-21 14:16:19 +01:00
Cedric Roux 668d7af7d2 align variables on stack in rank_estimation_tm3_tm4 
dlsim_tm4 was crashing on massive. It was a problem
of misalignment of variables. The generated code by
the compiler was using 'movdqa' which requires alignment
to 16 bytes. Let's put 32, just in case, for avx2 maybe
(maybe not necessary but should not hurt).
 2017-03-21 14:12:00 +01:00
Elena_Lukashova 79c304a24a Passing Conditional Number threshold as a command line argument. -V($) 2017-03-21 12:13:17 +01:00
Elena_Lukashova ca0d8a445e Fixing dlsch_demod_shift. 2017-03-21 12:03:23 +01:00
Calisson 98efcd5220 fixing a bug related to SRS procedures 2017-03-21 09:37:08 +01:00
Elena_Lukashova 93c1315bbd Adequate throughput computation for rank adaptation. 2017-03-21 02:13:08 +01:00
Calisson 1677e8f847 Merge remote-tracking branch 'origin/develop' into feature-218-srs 2017-03-20 17:15:26 +01:00
Calisson e2d46f8040 adding mechanism for SRS scheduling of multiple UEs. 2017-03-20 17:13:42 +01:00
Elena_Lukashova b596ede727 Merge remote-tracking branch 'origin/develop' into feature-59-tm4 2017-03-20 14:33:03 +01:00
Cedric Roux e2350103f4 hotfix: LLR was calling qam64_qam16_avx2 instead of qam64_qam64_avx2 
Not sure of this one, to be checked by TCL.
 2017-03-20 13:33:27 +01:00
Cedric Roux 1218cc8f65 bugfix: fix dump_dlsch2 
the argument 'coded_bits_per_codeword' has to be an array in
case of several codewords.

The calling sites have been adapted.

Today, only the first index is used, so calling sites where
'coded_bits_per_codeword' is an integer pass the address
of it. It is expected that 'dump_dlsch2' will check in the
future that there is one or two codewords and only access
'coded_bits_per_codeword[1]' when it's sure there are
really two codewords.
 2017-03-20 11:15:57 +01:00
Cedric Roux 7ffc20426b integration fix: let simulators compile again 
- pucchsim
- prachsim
- pdcchsim
- pbchsim
- mbmssim

Mostly, add and initialize the variable 'cpuf'.
Also, pdcchsim was calling rx_pdcch with wrong
arguments.
 2017-03-20 11:00:41 +01:00
Cedric Roux 5014b84c30 integration fix: let ulsim compile again + minor modification in dlsim_tm4 2017-03-20 10:43:50 +01:00
Cedric Roux f2e9e3f2dc integration fix: let dlsim compile again 
Same as previous commit 41dda3d3de
but for dlsim.
 2017-03-20 10:40:26 +01:00
Cedric Roux 41dda3d3de integration fix: let dlsim_tm4 compile again 
The variables that were duplicated per processing thread
were adapted. 'cpuf' was defined and initialized.
 2017-03-20 10:38:25 +01:00
gabrielC 1e2f952a9c Remove to frequent log in 20 MHz 2017-03-20 09:18:02 +01:00
Elena_Lukashova b835f63956 1. There is probably a bug in generate_ue_dlsch_from_dci 
for DCI format 2. Temporaryly going back to the previous
version of code.
2. Enabling rate adaptation with multiple HARQ rounds.
(no change inside the rounds).
 2017-03-20 01:06:12 +01:00
Elena_Lukashova a92ed31914 Merge branch 'develop' into feature-59-tm4 2017-03-19 15:52:45 +01:00
Cedric Roux 2011c7d689 Merge remote-tracking branch 'origin/ulsim-bugfix-w11' into develop_integration_w11 2017-03-18 00:10:50 +01:00
Cedric Roux 1c57eadd33 fix: remove useless test 
One check introduced by previous commit was not necessary.
 2017-03-18 00:09:48 +01:00
Cedric Roux 7847143610 Merge remote-tracking branch 'origin/bugfix-224-ue-tcrnti' into develop_integration_w11 2017-03-17 19:33:56 +01:00
fnabet 7f9b19cce8 UE Issue224 fix on TCRNTI 2017-03-17 10:52:59 +01:00
Florian Kaltenberger c13d5c21f3 added null pointer check for ulsim 2017-03-16 18:05:23 +01:00
Cedric Roux 639d2eefc6 Merge remote-tracking branch 'origin/phy-test-fix' into develop_integration_w11 2017-03-16 18:01:23 +01:00
gabrielC d5a9334306 20MHz improvement for scope (still need to be fixed for 20MHz LLR) and Log 2017-03-16 17:06:34 +01:00
gabrielC 950c1c060e Correction of dlsch channel calculation 2017-03-16 11:45:07 +01:00
Florian Kaltenberger 65f49f9ffd bugfixes to previous commit and ulsim. now srs estimaton seems to work. at least in ulsim. 2017-03-15 17:43:18 +01:00
Cedric Roux f5aa0135b1 hotfix: fix buffer size for phy-test mode 20MHz 
768*8 is too small, in 20MHz, the phy-test mode
(in default mode?) has a buffer of size 6378.

Let's set the buffer size to the input's one plus 4 bytes
(to accomodate for CRC, not sure about this).
 2017-03-15 17:17:54 +01:00
Calisson 1e193853eb WIP: adding srs channel estimation to eNB. estimation results yet to be checked. 2017-03-14 17:13:14 +01:00
gabrielC 752b305270 Merge branch 'pdcch_dual_buffer' into develop_integration_w11 2017-03-14 15:44:13 +01:00
gabrielC 28a50c15e9 Remove some print and correct rnti for the pdcch_vars odd/even subframe 2017-03-14 15:35:21 +01:00
Elena_Lukashova 488933eddc Removing unnecessary minus_one and plus_one. 2017-03-13 17:04:36 +01:00
hbilel bd4898222f pdcch dual buffer 2017-03-13 15:50:10 +01:00
Cedric Roux a500b2b293 integration fix: fix compilation of ulsim 
We use the odd/even dlsch corresponding to the configured
subframe. It may not be the right thing to do.
 2017-03-13 15:43:43 +01:00
Elena_Lukashova 21481c4a6a Adding check for the first transmission in prepare_dl_decoding_format1_1A. 2017-03-13 15:13:45 +01:00
hbilel cec9cb7662 fix compilation error for dlsim 2017-03-13 12:05:47 +01:00
hbilel b82b7781ee integration fix clear tx-buffer of ue in case of empty subframe 
for all processing including oaisim
 2017-03-13 10:14:26 +01:00
Cedric Roux a194009e00 integration fix: put dlsch_demod_shift into dlsch_demodulation 2017-03-13 10:06:26 +01:00
Elena_Lukashova e5908bfdaa Fixing a bug in conjch0_mult_ch1 2017-03-12 00:29:50 +01:00
Elena_Lukashova 14d927d414 Fixing TM condition for rank estimation. 
the eNB_id was overwriiten by the preceding loop
and setting ue->transmission_mode = 0.
 2017-03-11 19:25:15 +01:00