Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.
- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
optimizations for 128-bit to improve performance of LDPC encode/decode
on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
fix the 64QAM modulator case, that process 192 bits per iteration, then 24 bits per iteration of the tail bits, then added the last two symboles processing (no odd number of symbols case)
1. Adding a "SL" frequency for Sidelink mode. The
importance of this variable is to ensure that
when we are in mode 1 (UE+UE+gNB), that the slot
configuration and frequencies do not overlap. This
SL frequency is important for rotation and allows
us to utilize the OFDM modulation and demodulation
functions that already exist in OAI.
2. Adding sl_mode to the command line for proper UE
deployment when in SL mode. sl_mode can be set to 0,
1, or 2. sl_mode 0 indicates no-Sidelink at all,
mode 1 is gNB, UE, and UE (3GPP defines mode numbers).
sl_mode 2 indicated UE to UE communications with no
gNB at all.
3. New functions for calculating the carrier frequency
for SL mode.
- Added nr_dft at UE side and nr_idft at gNB side
- NR_SC_FDMA can be found in "PHY/defs_nr_common.h"
- For 1 SNR loop, the code executes correctly
- For more loops, it gives a segmentation fault in the LDPC decoder
- The segmentation fault is caused when nr_idft is used
- The code works fine when the "NR_SC_FDMA" is disabled
Quency Lin