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59086151e0bd1c7fbcd0103dbb982ee2fbe7433e
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745 Commits
Author SHA1 Message Date
francescomani 83c59b05e9 code cleanup and small fixes 2024-07-11 11:25:22 +02:00
Robert Schmidt 9f86e33ec2 Merge remote-tracking branch 'origin/t2-offload-mr4.1' into integration_2024_w27 2024-07-09 07:54:08 +02:00
Jaroslava Fiedlerova 432fee1a6e Configure T2 EAL Parameters via Command Line 
- Introduced command line and configuration options to set up PCI address, CPU cores used by DPDK, and DPDK file prefix for T2 offload.
- Made the dpdk_dev parameter (for setting the PCI address of the T2) mandatory.
- Configure dpdk_dev in the CI test cases.
 2024-06-27 14:53:17 +02:00
Jaroslava Fiedlerova fe0d70e8f3 Replace bbdev TEST_ASSERTs by OAI macro AssertFatal() 
- Replaced bbdev TEST_ASSERTs with the OAI macro AssertFatal() to harmonize error handling.
- Removed unused functions and macros from nrLDPC_offload.h.
 2024-06-27 14:47:32 +02:00
Jaroslava Fiedlerova 6bec8779c6 Enhance T2 Offload for gNB and UE 
- Reworked nrLDPC_decoder_offload.c to process all segments in a TB with a single call to LDPCdecoder() or LDPCencoder().
- Perform CRC checks on the T2.
- Modified nr_ulsch_decoding (gNB decoder) to:
  - Count processed segments.
  - Properly perform CRC checks.
- Created a constant NR_LDPC_MAX_NUM_CB to define the maximum number of codeblocks.
- Conditional library loading:
  - On gNB: Load ldpc_t2 library if offload is enabled using the --ldpc-offload-enable flag.
  - On UE: Load both ldpc_t2 and ldpc libraries since only encoder offload is supported.
- General cleanup of nrLDPC_decoder_offload.c for improved readability and maintainability.
- Modified the structure of LDPC encoder/decoder/offload parameters:
  - Introduced a structure for code block (CB) related parameters.
  - Removed parameter E from the encoder and offload parameter structures for clarity.
  - Replaced E with perCB->E_cb in the UE encoder code.
 2024-06-27 14:40:41 +02:00
Romain Beurdouche 327b9a8b70 fix(phy_simulators): enable the use of option -O to pass a configuration file to configmodule in phy simulators 2024-06-25 10:38:09 +02:00
Robert Schmidt d268378f2b Merge remote-tracking branch 'origin/fix_phy_simulators_configmodule' into integration_2024_w21c 2024-05-24 11:50:11 +02:00
Robert Schmidt 1465fed81c Merge remote-tracking branch 'origin/better-polar' into integration_2024_w21c 2024-05-24 11:50:04 +02:00
Romain Beurdouche b51a144d7d fix(phy simulators): fix cmdline configmodule for CODING phy simulators 2024-05-15 14:12:40 +02:00
francescomani 114fb5dbca bugfix in dci reception, CRC is 24 bits but uint16 was used 2024-04-30 12:36:15 +02:00
francescomani 90f82d19da remove false DCI reception indication 2024-04-29 12:39:44 +02:00
Laurent THOMAS ab2b868b75 improve polar init and polar readability 2024-04-24 15:26:21 +02:00
Robert Schmidt 24baf08c87 Load unaligned data for SIMD processing to avoid segv 
We access G_N at indexes that are not necessarily 32-byte aligned,
leading to segfaults. Use simde_mm256_loadu_si256() to load from memory
at an unaligned memory address to avoid the segfault.

Discovered using clang; it is unclear why gcc did not encounter the same
segfault.
 2024-04-18 14:06:05 +02:00
Robert Schmidt ebeb26528a Merge remote-tracking branch 'origin/NR_PSBCH_MERGE1' into integration_2024_w15 2024-04-15 14:34:36 +02:00
Robert Schmidt 9a2e080f77 Apply clang-format 2024-04-13 08:54:15 +02:00
Raghavendra Dinavahi 94b23d1eb0 PSBCH RX TX and SLSS search procedures 
- RX/TX Phy processing accg to 38.211, 38.212 Rel16
	- PSBCH simulator used to validate TX/RX phy processing
	- PSBCH SLSS Search procedures
	- PSBCH SIM also tests SLSS SEARCH
 2024-04-12 16:07:00 +02:00
Jaroslava Fiedlerova 87242ca92a Merge remote-tracking branch 'origin/fix_cppcheck' into integration_2024_w15 2024-04-12 09:18:07 +02:00
Jaroslava Fiedlerova 3c3c1e6fe6 T2 related modifications of CMakeLists and documentation 
- Modify T2 PCI adr for CI T2 test setup
- Set PKG_CONFIG_PATH env var manually if needed (DPDK lib installed into custom path)
 2024-04-11 15:34:43 +02:00
francescomani 8404da759f nullPointerRedundantCheck 2024-04-09 16:55:51 +02:00
francescomani 96ff859cb7 shiftTooManyBitsSigned 2024-04-09 16:53:12 +02:00
francescomani 9cc53a43b1 invalidPrintfArgType_uint 2024-04-09 16:44:56 +02:00
francescomani 686da85d05 invalidPrintfArgType_sint 2024-04-09 16:44:56 +02:00
Laurent a0e7733035 Warning fix to RHEL generated message 
: error: '<unknown>' may be used uninitialized [-Werror=maybe-uninitialized]
  180 |   reverse_bits_u8(tmp, N/8, D2);
 2024-04-05 14:14:18 +02:00
mir b21552973c Remove old OAI implementation 2024-03-22 11:36:45 +01:00
mir a6ad11a20e Remove duplicated bit reverse table 2024-03-22 11:36:41 +01:00
mir 44e31bd845 Improved polar encoder 2024-03-22 11:35:34 +01:00
mir 573e7d3a4a Comments from MR 2024-03-07 11:00:57 +01:00
mir fc8d0c59c6 Scan build: Result of operation is garbage or undefined 2024-03-07 11:00:57 +01:00
Jaroslava Fiedlerova b166286a78 Use clang format 2024-01-25 17:21:32 +01:00
Jaroslava Fiedlerova bec8ebc311 Perform interleaving on the T2 card 
- UE and gNB encoder modification
- update T2 related doc
 2024-01-25 17:21:32 +01:00
Jaroslava Fiedlerova aa9cd6394a T2: Enable LDPC encoding offload for all MCS 
- Rate matching performed by card
- Due to rate matching on card, small TBs are encoded correctly, so the
  limitation of encoding small TBs in CPU can be lifted (all TBs encoded
  on T2), see a later commits
 2024-01-25 17:21:11 +01:00
Laurent THOMAS 18919576b7 rework PUCCH codec with c16_t type, rewrite large parts of functions to make readable code. Not fixed parts that are using SIMD. No change, the code is still same block by block (variable visibility narrowed, declaration can be shifted) 2024-01-04 10:21:15 +01:00
Robert Schmidt cbff849b82 Merge remote-tracking branch 'origin/t2-offload-mr2' into integration_2023_w51 2023-12-21 16:14:02 +01:00
Jaroslava Fiedlerova c66b09c8a3 T2: Fix buffer overflow and HARQ codeblock ID out of range 
- set size of buffers to max E
- change HARQ codeblock offset calculation for T2
- add constant for maximum code block size - max E
 2023-12-21 11:19:13 +01:00
Robert Schmidt 6c2194038a Merge remote-tracking branch 'origin/enhance-polar-perf' into integration_2023_w49 2023-12-11 14:56:15 +01:00
Laurent THOMAS 175e835d05 update the polar codec function that creates the internal LUTs 
to use faster code
- replaced hundreds mallocs by either local arrays or by the OAI multi-dimensionalarray (G_N_tab array)
- made in SIMD a one bit per byte packing function to packed (ordinary) bits in bytes
 2023-12-08 17:11:16 +01:00
Jaroslava Fiedlerova 7c5b945766 Set RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE based on harq_to_be_cleared value 2023-11-28 09:37:37 +01:00
laurent 7bb529dcdf fix redundant member in ldpc decoder struct 2023-11-28 09:37:37 +01:00
laurent 10d7fe9cc6 fix regressions in cuda ldpc 2023-11-28 09:37:37 +01:00
Jaroslava Fiedlerova cf97acb8c7 Add T2 LDPC encoding/decoding offload 2023-11-28 09:37:37 +01:00
Laurent THOMAS 99ca87a1c1 Refactor LDPC API to make common API with various implementations 2023-11-28 09:37:37 +01:00
Jaroslava Fiedlerova e945b260f8 Remove T1 decoding offload 2023-11-28 09:37:37 +01:00
Laurent THOMAS f50d5f5a9b make multiple config instead of one implicit global 2023-11-10 10:23:11 +01:00
Robert Schmidt 7420de8fc9 Merge remote-tracking branch 'origin/fix-doxygen' into integration_2023_w43 2023-10-30 10:23:45 +01:00
Robert Schmidt 803fcb59a9 Merge remote-tracking branch 'origin/assigned_value_is_garbage_or_undefined' into integration_2023_w43 2023-10-30 10:22:03 +01:00
Robert Schmidt a51c5299c6 Merge remote-tracking branch 'origin/polar-encoder-perf-improv' into integration_2023_w43 2023-10-27 14:21:23 +02:00
Laurent THOMAS bba9aac079 fix most of doxygen warnings and errors 2023-10-26 16:47:19 +02:00
rmagueta e14903cd96 Call __builtin_popcountll function to count the number of bits set in uint64_t variable for polar codes 2023-10-26 12:23:20 +02:00
mir 2ccc58f6d3 Assigned value is garbage or undefined reportedt by scan-build 2023-10-25 11:51:33 +02:00
Raphael Defosseux 80c2bc3fcb fix(arm-build): immintrin.h is not available 
Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
 2023-10-20 11:36:39 +02:00