NR UE: fix PDCCH LLR indexing for different search space RB sizes
After !3603 (merged), when multiple search spaces have different CORESET
configurations (different number of RBs), the LLR buffer stride must be
calculated based on the maximum RB size across all search spaces, not the
current search space's RB size.
The LLR buffer is allocated with size based on get_pdcch_max_rbs(), but the
demapping function was using coreset_nbr_rb (current search space) for symbol
stride calculation, causing incorrect LLR extraction when search spaces have
different RB configurations.
This MR tries to fix it.
Closes#1021
When multiple search spaces have different CORESET configurations
(different number of RBs), the LLR buffer stride must be calculated
based on the maximum RB size across all search spaces, not the
current search space's RB size.
The LLR buffer is allocated with size based on get_pdcch_max_rbs(),
but the demapping function was using coreset_nbr_rb (current search
space) for symbol stride calculation, causing incorrect LLR extraction
when search spaces have different RB configurations.
1. Refactor PDCCH PHY functions to take rxdataF of one OFDM symbol and
produce LLR for each search space. The modified functions take
rxdataF in a different format than that produced by nr_slot_fep(). So
for now a memcpy is used to change the array structure. Once
nr_slot_fep() is modified, this memcpy will no longer be needed and
will be removed.
2. Modify DCI functions to decode DCI in the last PDCCH symbol and
inidcate to MAC once.
3. Fix PDCCH monitoring for start symbol > 0.
4. Fix multiple PDCCH monitoring within slot.
Co-authored-by: Sakthivel Velumani <mail@sakthi.me>
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.
- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
optimizations for 128-bit to improve performance of LDPC encode/decode
on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
As specified in TS 38.211 Section 7.3.2.3, c_init is the result of a mod
2^31. Before this commit, the code assumed a wrong, implicit mod 2^32,
even though the comment says otherwise.
francescomani