Elena_Lukashova
81215a2461
Fixing commit 21481c4a6a.
2017-03-28 16:40:08 +02:00
Elena_Lukashova
a0f40fd02b
Merge remote-tracking branch 'origin/develop' into feature-59-tm4
2017-03-27 14:03:51 +02:00
Elena_Lukashova
800f66b3d4
Fixing a bug in HARQ for SIC.
...
Now the llrs after SIC procedure are updated.
In dlsim_tm in case of TB0_active==-1,
the llr were taken from the wrong buffer, and in dlsch_demodulation
the SIC llrs were written into the wrong buffer in the same case.
2017-03-27 11:50:58 +02:00
Elena_Lukashova
e05a417cd2
Fixing previous commit
2017-03-26 20:17:47 +02:00
Elena_Lukashova
78bf45f3f3
Removing unnecessary arguments in SIC llr functions.
2017-03-25 18:18:42 +01:00
Cedric Roux
5485f131c3
bugfix: Rel14 was missing
2017-03-24 18:05:11 +01:00
Cedric Roux
fc5c876a81
Merge remote-tracking branch 'origin/feature-228-rrc-rel14' into develop_integration_w12
2017-03-24 17:08:27 +01:00
Cedric Roux
c54cb41805
Merge remote-tracking branch 'origin/various-fixes-w12' into develop_integration_w12
2017-03-24 17:07:26 +01:00
Cedric Roux
5db0548af0
bugfix
2017-03-24 16:55:30 +01:00
Cedric Roux
6448738e9b
bugfix/compilation warning removal in ulsim
2017-03-24 15:53:52 +01:00
Cedric Roux
583123e042
bugfix/compilation warning removal in dlsim
2017-03-24 15:49:19 +01:00
Cedric Roux
ac437d3d12
compilation warning removal
2017-03-24 12:30:06 +01:00
Cedric Roux
92ee6017cd
compilation warning removal
2017-03-24 12:09:09 +01:00
Cedric Roux
7514e7139a
compilation warning removal
2017-03-24 12:08:31 +01:00
Cedric Roux
048f07f67f
compilation warning removal
2017-03-24 12:07:51 +01:00
Cedric Roux
3ce5f50755
compilation warning removal
2017-03-24 12:03:56 +01:00
Cedric Roux
a3f7ceb395
compilation warning removal
2017-03-24 12:02:08 +01:00
Cedric Roux
1789b3de59
compilation warning removal
2017-03-24 12:00:58 +01:00
Cedric Roux
e82c6764f9
compilation warning removal
2017-03-24 12:00:23 +01:00
Cedric Roux
bf3a4f6464
compilation warning removal
2017-03-24 12:00:04 +01:00
Cedric Roux
d8627b5e3f
compilation warning removal
2017-03-24 11:59:27 +01:00
Cedric Roux
2291f4ebec
compilation warning removal
2017-03-24 11:58:01 +01:00
Cedric Roux
216cd0bf02
compilation warning removal
2017-03-24 11:56:34 +01:00
Cedric Roux
8dd8a97c34
compilation warning removal
2017-03-24 11:55:32 +01:00
Cedric Roux
11856c6b00
compilation warning removal: allocate_REs set but not used
...
I removed this variable entirely because it's not used.
Maybe the bug is that it's not used after being set?
To be checked and fixed at some point.
2017-03-24 11:53:34 +01:00
Cedric Roux
774452bbbb
compilation warning removal
...
this variable does not seem to be used, to be removed?
2017-03-24 11:50:56 +01:00
Cedric Roux
4fcb6272f4
RRC Rel14
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- import RRC ASN.1 defintions from the specifications
(file openair2/RRC/LITE/MESSAGES/asn1c/ASN1_files/RRC-e10.asn)
contrary to rel8/10, all modules have been imported, maybe it's too much
to refine in case of problems
- deal with rel14 in fix_asn1
- all code that was for Rel10 is now for Rel10/Rel14
- some incompatible changes (mostly in naming) were resolved in favor
of rel14, see in openair2/RRC/LITE/defs.h
- unsure about the rlc layer, some arrays have changed (values appended),
I only changed the definition and in tests in the code, I changed
the index limit, maybe it's not enough
Rel14 is the default compilation mode.
2017-03-23 18:06:40 +01:00
Elena_Lukashova
b88fec2304
Some more printouts for rank adaptation.
2017-03-21 23:15:24 +01:00
Elena_Lukashova
23109e1a82
Optimizing bler files for rank adaptation.
2017-03-21 21:06:25 +01:00
Elena_Lukashova
9d2a4717d0
Changing the bler computation and printouts for the rank adaptation in tm4.
...
Now it counts how many times the TBs were set to active.
2017-03-21 18:52:41 +01:00
Elena_Lukashova
6219ddc581
Rank adaptation is now an argument of the command line.
2017-03-21 15:17:42 +01:00
Calisson
9d3eed3b43
fixing ulsim
2017-03-21 15:02:20 +01:00
Elena_Lukashova
48d7a1ef3a
Fixing arguments of lte_ue_measurements in pbchsim.c
2017-03-21 14:35:32 +01:00
Calisson
7685cf1811
fixing srs in msg3. now all SRS subframe configs work.
2017-03-21 14:16:19 +01:00
Cedric Roux
668d7af7d2
align variables on stack in rank_estimation_tm3_tm4
...
dlsim_tm4 was crashing on massive. It was a problem
of misalignment of variables. The generated code by
the compiler was using 'movdqa' which requires alignment
to 16 bytes. Let's put 32, just in case, for avx2 maybe
(maybe not necessary but should not hurt).
2017-03-21 14:12:00 +01:00
Elena_Lukashova
79c304a24a
Passing Conditional Number threshold as a command line argument. -V($)
2017-03-21 12:13:17 +01:00
Elena_Lukashova
ca0d8a445e
Fixing dlsch_demod_shift.
2017-03-21 12:03:23 +01:00
Calisson
98efcd5220
fixing a bug related to SRS procedures
2017-03-21 09:37:08 +01:00
Elena_Lukashova
93c1315bbd
Adequate throughput computation for rank adaptation.
2017-03-21 02:13:08 +01:00
Calisson
1677e8f847
Merge remote-tracking branch 'origin/develop' into feature-218-srs
2017-03-20 17:15:26 +01:00
Calisson
e2d46f8040
adding mechanism for SRS scheduling of multiple UEs.
2017-03-20 17:13:42 +01:00
Elena_Lukashova
b596ede727
Merge remote-tracking branch 'origin/develop' into feature-59-tm4
2017-03-20 14:33:03 +01:00
Cedric Roux
e2350103f4
hotfix: LLR was calling qam64_qam16_avx2 instead of qam64_qam64_avx2
...
Not sure of this one, to be checked by TCL.
2017-03-20 13:33:27 +01:00
Cedric Roux
1218cc8f65
bugfix: fix dump_dlsch2
...
the argument 'coded_bits_per_codeword' has to be an array in
case of several codewords.
The calling sites have been adapted.
Today, only the first index is used, so calling sites where
'coded_bits_per_codeword' is an integer pass the address
of it. It is expected that 'dump_dlsch2' will check in the
future that there is one or two codewords and only access
'coded_bits_per_codeword[1]' when it's sure there are
really two codewords.
2017-03-20 11:15:57 +01:00
Cedric Roux
7ffc20426b
integration fix: let simulators compile again
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- pucchsim
- prachsim
- pdcchsim
- pbchsim
- mbmssim
Mostly, add and initialize the variable 'cpuf'.
Also, pdcchsim was calling rx_pdcch with wrong
arguments.
2017-03-20 11:00:41 +01:00
Cedric Roux
5014b84c30
integration fix: let ulsim compile again + minor modification in dlsim_tm4
2017-03-20 10:43:50 +01:00
Cedric Roux
f2e9e3f2dc
integration fix: let dlsim compile again
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Same as previous commit 41dda3d3de
2017-03-20 10:40:26 +01:00
Cedric Roux
41dda3d3de
integration fix: let dlsim_tm4 compile again
...
The variables that were duplicated per processing thread
were adapted. 'cpuf' was defined and initialized.
2017-03-20 10:38:25 +01:00
gabrielC
1e2f952a9c
Remove to frequent log in 20 MHz
2017-03-20 09:18:02 +01:00
Elena_Lukashova
b835f63956
1. There is probably a bug in generate_ue_dlsch_from_dci
...
for DCI format 2. Temporaryly going back to the previous
version of code.
2. Enabling rate adaptation with multiple HARQ rounds.
(no change inside the rounds).
2017-03-20 01:06:12 +01:00
Elena_Lukashova