Now the llrs after SIC procedure are updated. In dlsim_tm in case of TB0_active==-1, the llr were taken from the wrong buffer, and in dlsch_demodulation the SIC llrs were written into the wrong buffer in the same case.
This directory contains unitary testbenches/Monte Carlo Simulators for physical/transport channel processing: pbchsim.c // PBCH simulation testbench pdcchsim.c // PDCCH (DCI) simulation testbench, PCFICH + PHICH too (incomplete) dlsim.c // PDSCH simulation testbench ulsim.c // PUSCH simulation testbench pucchsim.c // PUCCH simulation testbench framegen.c // eNB Frame generator