181 lines
6.9 KiB
C
181 lines
6.9 KiB
C
/*
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* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership.
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* The OpenAirInterface Software Alliance licenses this file to You under
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* the OAI Public License, Version 1.1 (the "License"); you may not use this file
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* except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.openairinterface.org/?page_id=698
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*-------------------------------------------------------------------------------
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* For more information about the OpenAirInterface (OAI) Software Alliance:
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* contact@openairinterface.org
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*/
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/*! \file phy_procedures_lte_eNB.c
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* \brief Implementation of common utilities for eNB/UE procedures from 36.213 LTE specifications
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* \author R. Knopp, F. Kaltenberger
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* \date 2011
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* \version 0.1
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* \company Eurecom
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* \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr
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* \note
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* \warning
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*/
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#include "sched_nr.h"
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/// LUT for the number of symbols in the coreset indexed by coreset index (4 MSB rmsi_pdcch_config)
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uint8_t nr_coreset_nsymb_pdcch_type_0_b40Mhz[16] = {2,2,2,2,2,3,3,3,3,3,1,1,1,2,2,2}; // below 40Mhz bw
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uint8_t nr_coreset_nsymb_pdcch_type_0_a40Mhz[10] = {2,2,3,3,1,1,2,2,3,3}; // above 40Mhz bw
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/// LUT for the number of RBs in the coreset indexed by coreset index
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uint8_t nr_coreset_rb_offset_pdcch_type_0_b40Mhz[16] = {0,1,2,3,4,0,1,2,3,4,12,14,16,12,14,16};
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uint8_t nr_coreset_rb_offset_pdcch_type_0_a40Mhz[10] = {0,4,0,4,0,28,0,28,0,28};
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/// LUT for monitoring occasions param O indexed by ss index (4 LSB rmsi_pdcch_config)
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uint8_t nr_ss_param_O_type_0_mux1_FR1[16] = {0,0,2,2,5,5,7,7,0,5,0,0,2,2,5,5};
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uint8_t nr_ss_param_O_type_0_mux1_FR2[14] = {0,0,2.5,2.5,5,5,0,2.5,5,7.5,7.5,7.5,0,5};
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/// LUT for number of SS sets per slot indexed by ss index
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uint8_t nr_ss_sets_per_slot_type_0_FR1[16] = {1,2,1,2,1,2,1,2,1,1,1,1,1,1,1,1};
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uint8_t nr_ss_sets_per_slot_type_0_FR2[14] = {1,2,1,2,1,2,2,2,2,1,2,2,1,1};
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/// LUT for monitoring occasions param M indexed by ss index
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uint8_t nr_ss_param_M_type_0_mux1_FR1[16] = {1,0.5,1,0.5,1,0.5,1,0.5,2,2,1,1,1,1,1,1};
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uint8_t nr_ss_param_M_type_0_mux1_FR2[14] = {1,0.5,1,0.5,1,0.5,0.5,0.5,0.5,1,0.5,0.5,2,2};
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/// LUT for SS first symbol index indexed by ss index
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uint8_t nr_ss_first_symb_idx_type_0_mux1_FR1[8] = {0,0,1,2,1,2,1,2};
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nr_subframe_t nr_subframe_select(nfapi_nr_config_request_t *cfg,unsigned char subframe)
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{
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if (cfg->subframe_config.duplex_mode.value == FDD)
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return(SF_DL);
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}
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void nr_configure_css_dci_from_mib(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
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nr_scs_e scs_common,
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nr_scs_e pdcch_scs,
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nr_frequency_range_e freq_range,
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uint8_t rmsi_pdcch_config,
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uint8_t ssb_idx,
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uint16_t nb_slots_per_frame,
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uint16_t N_RB)
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{
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uint8_t O, M;
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uint8_t ss_idx = rmsi_pdcch_config&0xf;
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uint8_t cset_idx = (rmsi_pdcch_config>>4)&0xf;
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uint8_t mu;
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/// Coreset params
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switch(scs_common) {
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case kHz15:
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mu = 0;
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break;
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case kHz30:
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mu = 1;
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if (N_RB < 106) { // Minimum 40Mhz bandwidth not satisfied
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switch(pdcch_scs) {
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case kHz15:
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break;
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case kHz30:
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pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
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pdcch_params->n_rb = (cset_idx < 10)? 24 : 48;
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pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
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pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
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break;
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default:
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AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
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}
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}
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else {
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AssertFatal(ss_idx<10 ,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
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switch(pdcch_scs) {
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case kHz15:
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break;
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case kHz30:
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pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
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pdcch_params->n_rb = (cset_idx < 4)? 24 : 48;
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pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
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pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
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break;
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default:
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AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
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}
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}
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case kHz60:
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mu = 2;
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break;
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case kHz120:
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mu = 3;
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break;
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default:
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AssertFatal(1==0,"Invalid common subcarrier spacing %d\n", scs_common);
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}
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/// Search space params
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switch(pdcch_params->mux_pattern) {
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case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1:
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if (freq_range == nr_FR1) {
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O = nr_ss_param_O_type_0_mux1_FR1[ss_idx];
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pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx];
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M = nr_ss_param_M_type_0_mux1_FR1[ss_idx];
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pdcch_params->first_symbol = (ss_idx < 8)? ( (ss_idx&1)? pdcch_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8];
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}
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else {
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AssertFatal(ss_idx<14 ,"Invalid search space index for multiplexing type 1 and FR2 %d\n", ss_idx);
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O = nr_ss_param_O_type_0_mux1_FR2[ss_idx];
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pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx];
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M = nr_ss_param_M_type_0_mux1_FR2[ss_idx];
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pdcch_params->first_symbol = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0;
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}
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pdcch_params->nb_slots = 2;
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pdcch_params->sfn_mod2 = ((uint8_t)(floor( (O*pow(2, mu) + floor(ssb_idx*M)) / nb_slots_per_frame )) & 1)? 1 : 0;
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pdcch_params->first_slot = (uint8_t)(O*pow(2, mu) + floor(ssb_idx*M)) % nb_slots_per_frame;
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break;
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case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2:
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break;
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case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3:
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break;
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default:
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AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", pdcch_params->mux_pattern);
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}
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pdcch_params->config_type = NFAPI_NR_CSET_CONFIG_MIB_SIB1;
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pdcch_params->cr_mapping_type = NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED;
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pdcch_params->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE;
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pdcch_params->reg_bundle_size = 6;
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pdcch_params->interleaver_size = 2;
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}
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void nr_configure_css_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
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nfapi_nr_coreset_t* coreset,
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nfapi_nr_search_space_t* search_space) {
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}
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