gabrielC
ad6d0ac59e
bug fixes from Fujitsu (bug 37)
----------------------------------------------------------
bug 37
Ttile:
Sending side is as follows.
rar[3] = (((mcs&0x7)<<5)) | ((TPC&7)<<2) | ((ULdelay&1)<<1) | (cqireq&1);
So, 2 bit shift looks correct.
Bug Location:
ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>3)&7;//rar->TPC;
----------------------------------------------------------
2017-05-12 13:54:49 +02:00
..
2017-01-06 12:01:05 +08:00
2017-04-08 17:20:32 +02:00
2017-03-20 17:15:26 +01:00
2016-11-18 15:35:21 +01:00
2017-05-12 13:54:49 +02:00
2017-03-24 12:08:31 +01:00
2017-03-28 10:17:51 +08:00
2017-03-16 17:06:34 +01:00
2016-10-24 16:21:05 +02:00
2017-03-10 12:42:04 +01:00
2017-02-16 12:14:26 +01:00
2017-03-08 12:16:38 +01:00
2016-09-27 16:54:39 +02:00
2016-09-27 16:54:39 +02:00
2016-10-11 18:52:14 +02:00