Consider retransmissions in the preprocessor
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@@ -513,45 +513,79 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
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module_id, UE_id, frame, slot, num_slots_per_tdd, &sched_ctrl->pucch_sched_idx);
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AssertFatal(sched_ctrl->pucch_sched_idx >= 0, "no uplink slot for PUCCH found!\n");
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// Time-domain allocation
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sched_ctrl->time_domain_allocation = 2;
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// Freq-demain allocation
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uint8_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
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const int current_harq_pid = sched_ctrl->current_harq_pid;
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NR_UE_harq_t *harq = &sched_ctrl->harq_processes[current_harq_pid];
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NR_UE_ret_info_t *retInfo = &sched_ctrl->retInfo[current_harq_pid];
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const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
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int rbStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
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while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
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int rbSize = 1;
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while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize]) rbSize++;
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DevAssert(rbSize >= 3); /* just ensure we have at least 3 RBs */
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sched_ctrl->rbSize = rbSize;
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sched_ctrl->rbStart = rbStart;
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if (harq->round != 0) { /* retransmission */
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sched_ctrl->time_domain_allocation = retInfo->time_domain_allocation;
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/* ensure that there is a free place for RB allocation */
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int rbSize = 0;
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while (rbSize < retInfo->rbSize) {
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rbStart += rbSize; /* last iteration rbSize was not enough, skip it */
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rbSize = 0;
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while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
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if (rbStart >= bwpSize) {
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LOG_E(MAC,
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"cannot allocate retransmission for UE %d/RNTI %04x: no resources\n",
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UE_id,
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rnti);
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return;
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}
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while (rbStart + rbSize < bwpSize
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&& !vrb_map[rbStart + rbSize]
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&& rbSize < retInfo->rbSize)
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rbSize++;
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}
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sched_ctrl->rbSize = retInfo->rbSize;
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sched_ctrl->rbStart = rbStart;
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/* MCS etc: just reuse from previous scheduling opportunity */
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sched_ctrl->mcsTableIdx = retInfo->mcsTableIdx;
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sched_ctrl->mcs = retInfo->mcs;
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sched_ctrl->numDmrsCdmGrpsNoData = retInfo->numDmrsCdmGrpsNoData;
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} else {
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// Time-domain allocation
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sched_ctrl->time_domain_allocation = 2;
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// Freq-demain allocation
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while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
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int rbSize = 1;
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while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize]) rbSize++;
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DevAssert(rbSize >= 3); /* just ensure we have at least 3 RBs */
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sched_ctrl->rbSize = rbSize;
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sched_ctrl->rbStart = rbStart;
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// modulation scheme
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sched_ctrl->mcsTableIdx = 0;
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sched_ctrl->mcs = 9;
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sched_ctrl->numDmrsCdmGrpsNoData = 1;
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uint8_t N_PRB_DMRS =
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getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData);
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int nrOfSymbols = getNrOfSymbols(sched_ctrl->active_bwp,
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sched_ctrl->time_domain_allocation);
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const uint32_t TBS =
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nr_compute_tbs(nr_get_Qm_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
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nr_get_code_rate_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
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sched_ctrl->rbSize,
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nrOfSymbols,
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N_PRB_DMRS, // FIXME // This should be multiplied by the
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// number of dmrs symbols
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0 /* N_PRB_oh, 0 for initialBWP */,
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0 /* tb_scaling */,
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1 /* nrOfLayers */)
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>> 3;
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AssertFatal(TBS != 0, "TBS is zero but requested %d RBs!\n", sched_ctrl->rbSize);
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}
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/* mark the corresponding RBs as used */
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for (int rb = 0; rb < sched_ctrl->rbSize; rb++)
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vrb_map[rb + sched_ctrl->rbStart] = 1;
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// modulation scheme
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sched_ctrl->mcsTableIdx = 0;
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sched_ctrl->mcs = 9;
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sched_ctrl->numDmrsCdmGrpsNoData = 1;
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uint8_t N_PRB_DMRS =
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getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData);
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int nrOfSymbols = getNrOfSymbols(sched_ctrl->active_bwp,
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sched_ctrl->time_domain_allocation);
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const uint32_t TBS =
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nr_compute_tbs(nr_get_Qm_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
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nr_get_code_rate_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
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sched_ctrl->rbSize,
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nrOfSymbols,
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N_PRB_DMRS, // FIXME // This should be multiplied by the
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// number of dmrs symbols
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0 /* N_PRB_oh, 0 for initialBWP */,
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0 /* tb_scaling */,
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1 /* nrOfLayers */)
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>> 3;
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AssertFatal(TBS != 0, "TBS is zero but requested %d RBs!\n", sched_ctrl->rbSize);
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}
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void nr_schedule_ue_spec(module_id_t module_id,
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