removing calculate_preferred_dl_tda
This commit is contained in:
@@ -591,21 +591,9 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
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if (CellGroup) {
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if (get_softmodem_params()->sa) {
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calculate_preferred_dl_tda(Mod_idP, NULL);
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}
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const NR_ServingCellConfig_t *servingCellConfig = NULL;
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if(CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated) {
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servingCellConfig = CellGroup->spCellConfig->spCellConfigDedicated;
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const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig->downlinkBWP_ToAddModList;
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if(bwpList) {
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AssertFatal(bwpList->list.count > 0, "downlinkBWP_ToAddModList has no BWPs!\n");
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for (int i = 0; i < bwpList->list.count; ++i) {
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const NR_BWP_Downlink_t *bwp = bwpList->list.array[i];
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calculate_preferred_dl_tda(Mod_idP, bwp);
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}
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}
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const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList;
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if(ubwpList) {
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@@ -53,105 +53,25 @@
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#define WORD 32
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//#define SIZE_OF_POINTER sizeof (void *)
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void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *bwp) {
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gNB_MAC_INST *nrmac = RC.nrmac[module_id];
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const int bwp_id = bwp ? bwp->bwp_Id : 0;
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const int set_dl_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int slot) {
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if (nrmac->preferred_dl_tda[bwp_id])
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return;
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/* there is a mixed slot only when in TDD */
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NR_ServingCellConfigCommon_t *scc = nrmac->common_channels->ServingCellConfigCommon;
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frame_type_t frame_type = nrmac->common_channels->frame_type;
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const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
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const NR_TDD_UL_DL_Pattern_t *tdd =
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scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
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int symb_dlMixed = 0;
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int nr_mix_slots = 0;
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int nr_slots_period = n;
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scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
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if (tdd) {
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symb_dlMixed = (1 << tdd->nrofDownlinkSymbols) - 1;
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nr_mix_slots = tdd->nrofDownlinkSymbols != 0 || tdd->nrofUplinkSymbols != 0;
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nr_slots_period /= get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity);
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} else
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int nr_mix_slots = tdd->nrofDownlinkSymbols != 0; // there are dl symbols in mixed slot
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if (nr_mix_slots != 0) { // if there is a mixed slot
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int nr_slots_period = n/get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity);
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if ((slot%nr_slots_period) == tdd->nrofDownlinkSlots)
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return 1;
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}
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}
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else
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// if TDD configuration is not present and the band is not FDD, it means it is a dynamic TDD configuration
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AssertFatal(nrmac->common_channels->frame_type == FDD,"Dynamic TDD not handled yet\n");
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int target_ss;
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if (bwp) {
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target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
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} else {
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target_ss = NR_SearchSpace__searchSpaceType_PR_common;
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}
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const NR_SIB1_t *sib1 = nrmac->common_channels[0].sib1 ? nrmac->common_channels[0].sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL;
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NR_SearchSpace_t *search_space = get_searchspace(sib1,
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scc,
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bwp ? bwp->bwp_Dedicated : NULL,
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target_ss);
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NR_ControlResourceSet_t *coreset = get_coreset(module_id, scc, bwp ? bwp->bwp_Dedicated : NULL, search_space, target_ss);
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// get coreset symbol "map"
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const uint16_t symb_coreset = (1 << coreset->duration) - 1;
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NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList = get_pdsch_TimeDomainAllocationList(bwp,
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scc,
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sib1);
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AssertFatal(tdaList->list.count >= 1, "need to have at least one TDA for DL slots\n");
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/* check that TDA index 0 fits into DL and does not overlap CORESET */
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const NR_PDSCH_TimeDomainResourceAllocation_t *tdaP_DL = tdaList->list.array[0];
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AssertFatal(!tdaP_DL->k0 || *tdaP_DL->k0 == 0,
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"TimeDomainAllocation at index 1: non-null k0 (%ld) is not supported by the scheduler\n",
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*tdaP_DL->k0);
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int start, len;
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SLIV2SL(tdaP_DL->startSymbolAndLength, &start, &len);
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const uint16_t symb_tda = ((1 << len) - 1) << start;
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// check whether coreset and TDA overlap: then we cannot use it. Note that
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// here we assume that the coreset is scheduled every slot (which it
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// currently is) and starting at symbol 0
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AssertFatal((symb_coreset & symb_tda) == 0, "TDA index 0 for DL overlaps with CORESET\n");
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/* check that TDA index 1 fits into DL part of mixed slot, if it exists */
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int tdaMi = -1;
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if (frame_type == TDD && tdaList->list.count > 1) {
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const NR_PDSCH_TimeDomainResourceAllocation_t *tdaP_Mi = tdaList->list.array[1];
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AssertFatal(!tdaP_Mi->k0 || *tdaP_Mi->k0 == 0,
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"TimeDomainAllocation at index 1: non-null k0 (%ld) is not supported by the scheduler\n",
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*tdaP_Mi->k0);
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int start, len;
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SLIV2SL(tdaP_Mi->startSymbolAndLength, &start, &len);
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const uint16_t symb_tda = ((1 << len) - 1) << start;
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// check whether coreset and TDA overlap: then, we cannot use it. Also,
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// check whether TDA is entirely within mixed slot DL. Note that
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// here we assume that the coreset is scheduled every slot (which it
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// currently is)
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if ((symb_coreset & symb_tda) == 0 && (symb_dlMixed & symb_tda) == symb_tda) {
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tdaMi = 1;
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} else {
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LOG_E(MAC,
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"TDA index 1 DL overlaps with CORESET or is not entirely in mixed slot (symb_coreset %x symb_dlMixed %x symb_tda %x), won't schedule DL mixed slot\n",
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symb_coreset,
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symb_dlMixed,
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symb_tda);
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}
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}
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nrmac->preferred_dl_tda[bwp_id] = malloc(n * sizeof(*nrmac->preferred_dl_tda[bwp_id]));
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for (int i = 0; i < n; ++i) {
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nrmac->preferred_dl_tda[bwp_id][i] = -1;
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if (frame_type == FDD || i % nr_slots_period < tdd->nrofDownlinkSlots)
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nrmac->preferred_dl_tda[bwp_id][i] = 0;
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else if (nr_mix_slots && i % nr_slots_period == tdd->nrofDownlinkSlots)
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nrmac->preferred_dl_tda[bwp_id][i] = tdaMi;
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LOG_D(MAC, "slot %d preferred_dl_tda %d\n", i, nrmac->preferred_dl_tda[bwp_id][i]);
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}
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return 0; // if FDD or not mixed slot in TDD, for now use default TDA (TODO handle CSI-RS slots)
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}
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// Compute and write all MAC CEs and subheaders, and return number of written
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@@ -536,7 +456,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
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int current_harq_pid) {
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gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
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const NR_ServingCellConfigCommon_t *scc = nr_mac->common_channels->ServingCellConfigCommon;
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NR_ServingCellConfigCommon_t *scc = nr_mac->common_channels->ServingCellConfigCommon;
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NR_UE_info_t *UE_info = &nr_mac->UE_info;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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NR_sched_pdsch_t *retInfo = &sched_ctrl->harq_processes[current_harq_pid].sched_pdsch;
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@@ -566,7 +486,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
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int rbStart = 0; // start wrt BWPstart
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NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
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int rbSize = 0;
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const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot];
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const int tda = set_dl_tda(RC.nrmac[module_id], scc, slot);
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AssertFatal(tda>=0,"Unable to find PDSCH time domain allocation in list\n");
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if (tda == retInfo->time_domain_allocation) {
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@@ -910,7 +830,7 @@ void pf_dl(module_id_t module_id,
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if (max_num_ue < 0) return;
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/* MCS has been set above */
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const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot];
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const int tda = set_dl_tda(RC.nrmac[module_id], scc, slot);
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AssertFatal(tda>=0,"Unable to find PDSCH time domain allocation in list\n");
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NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
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NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
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@@ -982,12 +902,7 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
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/* This is temporary and it assumes all UEs have the same BWP and TDA*/
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int UE_id = UE_info->list.head;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0;
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if (!RC.nrmac[module_id]->preferred_dl_tda[bwp_id])
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return;
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const int tda = RC.nrmac[module_id]->preferred_dl_tda[bwp_id][slot];
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const int tda = set_dl_tda(RC.nrmac[module_id], scc, slot);
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int startSymbolIndex, nrOfSymbols;
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const struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList = sched_ctrl->active_bwp ?
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sched_ctrl->active_bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList :
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@@ -275,7 +275,8 @@ void nr_preprocessor_phytest(module_id_t module_id,
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__func__,
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UE_id);
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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const int tda = sched_ctrl->active_bwp ? RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot] : 1;
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const int tda = set_dl_tda(RC.nrmac[module_id], scc, slot);
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NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
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ps->nrOfLayers = target_dl_Nl;
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if (ps->time_domain_allocation != tda || ps->nrOfLayers != target_dl_Nl)
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@@ -2858,6 +2858,7 @@ void nr_csirs_scheduling(int Mod_idP,
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void nr_mac_update_timers(module_id_t module_id,
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frame_t frame,
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sub_frame_t slot) {
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NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
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const NR_list_t *UE_list = &UE_info->list;
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for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
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@@ -2894,12 +2895,11 @@ void nr_mac_update_timers(module_id_t module_id,
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cg->spCellConfig &&
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cg->spCellConfig->spCellConfigDedicated ?
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cg->spCellConfig->spCellConfigDedicated->initialDownlinkBWP : NULL;
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int **preferred_dl_tda = RC.nrmac[module_id]->preferred_dl_tda;
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NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
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const uint8_t layers = set_dl_nrOfLayers(sched_ctrl);
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const int tda = bwp && preferred_dl_tda[bwp->bwp_Id][slot] >= 0 ?
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preferred_dl_tda[bwp->bwp_Id][slot] : (ps->time_domain_allocation >= 0 ? ps->time_domain_allocation : 0);
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const int tda = set_dl_tda(RC.nrmac[module_id], scc, slot);
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nr_set_pdsch_semi_static(sib1,
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scc,
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@@ -522,7 +522,7 @@ void set_dl_mcs(NR_sched_pdsch_t *sched_pdsch,
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uint8_t set_dl_nrOfLayers(NR_UE_sched_ctrl_t *sched_ctrl);
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int get_dci_format(NR_UE_sched_ctrl_t *sched_ctrl);
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void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *bwp);
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const int set_dl_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int slot);
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void calculate_preferred_ul_tda(module_id_t module_id, const NR_BWP_Uplink_t *ubwp);
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bool find_free_CCE(module_id_t module_id, sub_frame_t slot, int UE_id);
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@@ -807,9 +807,6 @@ typedef struct gNB_MAC_INST_s {
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/// bitmap of DLSCH slots, can hold up to 160 slots
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uint64_t dlsch_slot_bitmap[3];
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/// Lookup for preferred time domain allocation for BWP, in DL, slots
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/// dynamically allocated
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int *preferred_dl_tda[MAX_NUM_BWP];
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/// bitmap of ULSCH slots, can hold up to 160 slots
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uint64_t ulsch_slot_bitmap[3];
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/// Lookup for preferred time domain allocation for UL BWP, dynamically
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@@ -321,8 +321,7 @@ void nr_rrc_config_dl_tda(NR_ServingCellConfigCommon_t *scc,
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int len_coreset = 1;
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if (curr_bwp < 48)
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len_coreset = 2;
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// setting default TDA for DL with
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// setting default TDA for DL with TDA index 0
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struct NR_PDSCH_TimeDomainResourceAllocation *timedomainresourceallocation = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
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// k0: Slot offset between DCI and its scheduled PDSCH (see TS 38.214 clause 5.1.2.1) When the field is absent the UE applies the value 0.
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//timedomainresourceallocation->k0 = calloc(1,sizeof(*timedomainresourceallocation->k0));
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@@ -331,10 +330,10 @@ void nr_rrc_config_dl_tda(NR_ServingCellConfigCommon_t *scc,
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timedomainresourceallocation->startSymbolAndLength = get_SLIV(len_coreset,14-len_coreset); // basic slot configuration starting in symbol 1 til the end of the slot
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ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation);
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if(frame_type==TDD) {
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// TDD
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if(scc->tdd_UL_DL_ConfigurationCommon) {
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int dl_symb = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols;
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if(dl_symb > 1) {
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// mixed slot TDA with TDA index 1
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timedomainresourceallocation = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
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// k0: Slot offset between DCI and its scheduled PDSCH (see TS 38.214 clause 5.1.2.1) When the field is absent the UE applies the value 0.
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//timedomainresourceallocation->k0 = calloc(1,sizeof(*timedomainresourceallocation->k0));
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