maki/openairinterface5g
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

nr_dlsim_preprocessor(): Refactor NR_sched_pdsch usage

Browse Source 
Similarly to parent commit(s), assign sched_pdsch in a single place
instead of relying on sched_ctrl. In a follow-up commit, the
post-processor will be called in a single place.
This commit is contained in:
Robert Schmidt
2025-10-30 19:14:06 +01:00
parent 1900edb56d
commit 4eb43f2c45
1 changed files with 29 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair1/SIMULATION/NR_PHY/dlsim.c
+29 -26
View File
@@ -213,46 +213,47 @@ void nr_dlsim_preprocessor(module_id_t module_id, frame_t frame, slot_t slot)
AssertFatal(CCEIndex>=0, "%4d.%2d could not find CCE for DL DCI UE %d/RNTI %04x\n", frame, slot, 0, UE_info->rnti);
sched_ctrl->cce_index = CCEIndex;
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
sched_pdsch->rbStart = g_rbStart;
sched_pdsch->rbSize = g_rbSize;
sched_pdsch->bwp_info = get_pdsch_bwp_start_size(RC.nrmac[module_id], UE_info);
sched_pdsch->mcs = g_mcsIndex;
sched_pdsch->nrOfLayers = g_nrOfLayers;
sched_pdsch->pm_index = g_pmi;
NR_sched_pdsch_t sched_pdsch = {
.rbStart = g_rbStart,
.rbSize = g_rbSize,
.bwp_info = get_pdsch_bwp_start_size(RC.nrmac[module_id], UE_info),
.mcs = g_mcsIndex,
.nrOfLayers = g_nrOfLayers,
.pm_index = g_pmi,
};
/* the following might override the table that is mandated by RRC
* configuration */
current_BWP->mcsTableIdx = g_mcsTableIdx;
sched_pdsch->time_domain_allocation = get_dl_tda(RC.nrmac[module_id], slot);
AssertFatal(sched_pdsch->time_domain_allocation >= 0,"Unable to find PDSCH time domain allocation in list\n");
sched_pdsch.time_domain_allocation = get_dl_tda(RC.nrmac[module_id], slot);
AssertFatal(sched_pdsch.time_domain_allocation >= 0,"Unable to find PDSCH time domain allocation in list\n");
sched_pdsch->tda_info = get_dl_tda_info(current_BWP,
sched_pdsch.tda_info = get_dl_tda_info(current_BWP,
sched_ctrl->search_space->searchSpaceType->present,
sched_pdsch->time_domain_allocation,
sched_pdsch.time_domain_allocation,
NR_MIB__dmrs_TypeA_Position_pos2,
1,
TYPE_C_RNTI_,
sched_ctrl->coreset->controlResourceSetId,
false);
sched_pdsch->dmrs_parms = get_dl_dmrs_params(scc,
sched_pdsch.dmrs_parms = get_dl_dmrs_params(scc,
current_BWP,
&sched_pdsch->tda_info,
sched_pdsch->nrOfLayers);
&sched_pdsch.tda_info,
sched_pdsch.nrOfLayers);
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx);
sched_pdsch->tb_size = nr_compute_tbs(sched_pdsch->Qm,
sched_pdsch->R,
sched_pdsch->rbSize,
sched_pdsch->tda_info.nrOfSymbols,
sched_pdsch->dmrs_parms.N_PRB_DMRS * sched_pdsch->dmrs_parms.N_DMRS_SLOT,
sched_pdsch.Qm = nr_get_Qm_dl(sched_pdsch.mcs, current_BWP->mcsTableIdx);
sched_pdsch.R = nr_get_code_rate_dl(sched_pdsch.mcs, current_BWP->mcsTableIdx);
sched_pdsch.tb_size = nr_compute_tbs(sched_pdsch.Qm,
sched_pdsch.R,
sched_pdsch.rbSize,
sched_pdsch.tda_info.nrOfSymbols,
sched_pdsch.dmrs_parms.N_PRB_DMRS * sched_pdsch.dmrs_parms.N_DMRS_SLOT,
0 /* N_PRB_oh, 0 for initialBWP */,
0 /* tb_scaling */,
sched_pdsch->nrOfLayers) >> 3;
sched_pdsch.nrOfLayers) >> 3;
/* the simulator assumes the HARQ PID is equal to the slot number */
sched_pdsch->dl_harq_pid = slot;
sched_pdsch.dl_harq_pid = slot;
/* The scheduler uses lists to track whether a HARQ process is
* free/busy/awaiting retransmission, and updates the HARQ process states.
@@ -266,10 +267,12 @@ void nr_dlsim_preprocessor(module_id_t module_id, frame_t frame, slot_t slot)
else
add_front_nr_list(&sched_ctrl->retrans_dl_harq, slot); // ... make PID retransmission
sched_ctrl->harq_processes[slot].is_waiting = false;
AssertFatal(sched_pdsch->rbStart >= 0, "invalid rbStart %d\n", sched_pdsch->rbStart);
AssertFatal(sched_pdsch->rbSize > 0, "invalid rbSize %d\n", sched_pdsch->rbSize);
AssertFatal(sched_pdsch->mcs >= 0, "invalid mcs %d\n", sched_pdsch->mcs);
AssertFatal(sched_pdsch.rbStart >= 0, "invalid rbStart %d\n", sched_pdsch.rbStart);
AssertFatal(sched_pdsch.rbSize > 0, "invalid rbSize %d\n", sched_pdsch.rbSize);
AssertFatal(sched_pdsch.mcs >= 0, "invalid mcs %d\n", sched_pdsch.mcs);
AssertFatal(current_BWP->mcsTableIdx >= 0 && current_BWP->mcsTableIdx <= 2, "invalid mcsTableIdx %d\n", current_BWP->mcsTableIdx);
sched_ctrl->sched_pdsch = sched_pdsch;
}
nrUE_params_t nrUE_params;