fixed issue with default CPU cores for RU in CI (now defaults to 2 TP cores and O/S controlled scheduling)
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+1
-1
@@ -63,7 +63,7 @@ unsigned short config_frames[4] = {2,9,11,13};
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static int DEFBANDS[] = {7};
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static int DEFENBS[] = {0};
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static int DEFBFW[] = {0x00007fff};
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static int DEFRUTPCORES[] = {2,4,6,8};
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static int DEFRUTPCORES[] = {-1,-1,-1,-1};
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//static int DEFNRBANDS[] = {7};
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//static int DEFGNBS[] = {0};
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@@ -201,7 +201,7 @@ typedef enum {
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{CONFIG_STRING_RU_RXFH_CORE_ID, HLP_RU_RXFH_CORE_ID, 0, uptr:NULL, defintval:0, TYPE_UINT, 0}, \
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{CONFIG_STRING_RU_TXFH_CORE_ID, HLP_RU_TXFH_CORE_ID, 0, uptr:NULL, defintval:0, TYPE_UINT, 0}, \
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{CONFIG_STRING_RU_TP_CORES, HLP_RU_TP_CORES, 0, uptr:NULL, defintarrayval:DEFRUTPCORES, TYPE_INTARRAY, 8}, \
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{CONFIG_STRING_RU_NUM_TP_CORES, HLP_RU_NUM_TP_CORES, 0, uptr:NULL, defintval:4, TYPE_UINT, 0}, \
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{CONFIG_STRING_RU_NUM_TP_CORES, HLP_RU_NUM_TP_CORES, 0, uptr:NULL, defintval:2, TYPE_UINT, 0}, \
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{CONFIG_STRING_RU_NUM_INTERFACES, HLP_RU_NUM_INTERFACES, 0, uptr:NULL, defintval:1, TYPE_UINT, 0}, \
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{CONFIG_STRING_RU_HALF_SLOT_PARALLELIZATION, HLP_RU_HALF_SLOT_PARALLELIZATION, 0, uptr:NULL, defintval:1, TYPE_UINT, 0}, \
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}
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