allocate only necessary amount of RBs
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@@ -552,35 +552,36 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
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// Time-domain allocation
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sched_ctrl->time_domain_allocation = 2;
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// Freq-demain allocation
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while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
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int rbSize = 1;
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while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize]) rbSize++;
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DevAssert(rbSize >= 3); /* just ensure we have at least 3 RBs */
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sched_ctrl->rbSize = rbSize;
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sched_ctrl->rbStart = rbStart;
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// modulation scheme
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sched_ctrl->mcsTableIdx = 0;
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sched_ctrl->mcs = 9;
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sched_ctrl->numDmrsCdmGrpsNoData = 1;
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// Freq-demain allocation
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while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
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uint8_t N_PRB_DMRS =
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getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData);
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int nrOfSymbols = getNrOfSymbols(sched_ctrl->active_bwp,
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sched_ctrl->time_domain_allocation);
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const uint32_t TBS =
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nr_compute_tbs(nr_get_Qm_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
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nr_get_code_rate_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
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sched_ctrl->rbSize,
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nrOfSymbols,
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N_PRB_DMRS, // FIXME // This should be multiplied by the
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// number of dmrs symbols
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0 /* N_PRB_oh, 0 for initialBWP */,
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0 /* tb_scaling */,
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1 /* nrOfLayers */)
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>> 3;
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AssertFatal(TBS != 0, "TBS is zero but requested %d RBs!\n", sched_ctrl->rbSize);
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int rbSize = 0;
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uint32_t TBS = 0;
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do {
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rbSize++;
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TBS = nr_compute_tbs(nr_get_Qm_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
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nr_get_code_rate_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
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rbSize,
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nrOfSymbols,
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N_PRB_DMRS, // FIXME // This should be multiplied by the
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// number of dmrs symbols
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0 /* N_PRB_oh, 0 for initialBWP */,
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0 /* tb_scaling */,
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1 /* nrOfLayers */)
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>> 3;
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} while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize] && TBS < sched_ctrl->num_total_bytes);
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sched_ctrl->rbSize = rbSize;
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sched_ctrl->rbStart = rbStart;
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}
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/* mark the corresponding RBs as used */
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