removing calculate_preferred_ul_tda
This commit is contained in:
@@ -592,19 +592,9 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
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if (CellGroup) {
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const NR_ServingCellConfig_t *servingCellConfig = NULL;
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if(CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated) {
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if(CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
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servingCellConfig = CellGroup->spCellConfig->spCellConfigDedicated;
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const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList;
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if(ubwpList) {
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AssertFatal(ubwpList->list.count > 0, "uplinkBWP_ToAddModList no BWPs!\n");
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for (int i = 0; i < ubwpList->list.count; ++i) {
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const NR_BWP_Uplink_t *ubwp = ubwpList->list.array[i];
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calculate_preferred_ul_tda(Mod_idP, ubwp);
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}
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}
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}
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NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
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if (add_ue == 1 && get_softmodem_params()->phy_test) {
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const int UE_id = add_new_nr_ue(Mod_idP, rnti, CellGroup);
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@@ -60,8 +60,7 @@ const int set_dl_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int
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scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
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if (tdd) {
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int nr_mix_slots = tdd->nrofDownlinkSymbols != 0; // there are dl symbols in mixed slot
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if (nr_mix_slots != 0) { // if there is a mixed slot
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if (tdd->nrofDownlinkSymbols > 1) { // if there is a mixed slot where we can transmit DL
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int nr_slots_period = n/get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity);
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if ((slot%nr_slots_period) == tdd->nrofDownlinkSlots)
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return 1;
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@@ -436,7 +436,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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const int tda = sched_ctrl->active_ubwp ? RC.nrmac[module_id]->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot] : 1;
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const int tda = set_ul_tda(nr_mac, scc, slot);
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if (tda < 0)
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return false;
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const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
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@@ -2917,14 +2917,13 @@ void nr_mac_update_timers(module_id_t module_id,
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cg->spCellConfig->spCellConfigDedicated &&
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cg->spCellConfig->spCellConfigDedicated->uplinkConfig ?
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cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP : NULL;
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int **preferred_ul_tda = RC.nrmac[module_id]->preferred_ul_tda;
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NR_pusch_semi_static_t *ups = &sched_ctrl->pusch_semi_static;
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int dci_format = get_dci_format(sched_ctrl);
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const uint8_t num_dmrs_cdm_grps_no_data = (ubwp || ubwpd) ? 1 : 2;
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const uint8_t nrOfLayers = 1;
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const int utda = ubwp && preferred_ul_tda[ubwp->bwp_Id][slot] >= 0 ?
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preferred_ul_tda[ubwp->bwp_Id][slot] : (ups->time_domain_allocation >= 0 ? ups->time_domain_allocation : 0);
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const int utda = set_ul_tda(RC.nrmac[module_id], scc, slot);
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nr_set_pusch_semi_static(sib1,
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scc,
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@@ -46,138 +46,25 @@ int get_dci_format(NR_UE_sched_ctrl_t *sched_ctrl) {
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return(dci_format);
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}
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void calculate_preferred_ul_tda(module_id_t module_id, const NR_BWP_Uplink_t *ubwp)
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{
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gNB_MAC_INST *nrmac = RC.nrmac[module_id];
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const int bwp_id = ubwp->bwp_Id;
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if (nrmac->preferred_ul_tda[bwp_id])
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return;
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const int set_ul_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int slot) {
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/* there is a mixed slot only when in TDD */
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NR_ServingCellConfigCommon_t *scc = nrmac->common_channels->ServingCellConfigCommon;
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frame_type_t frame_type = nrmac->common_channels->frame_type;
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const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
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const NR_TDD_UL_DL_Pattern_t *tdd =
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scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
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NR_ServingCellConfigCommonSIB_t *scc_sib1 = nrmac->common_channels[0].sib1 ?
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RC.nrmac[module_id]->common_channels[0].sib1->message.choice.c1->choice.systemInformationBlockType1->servingCellConfigCommon : NULL;
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AssertFatal(scc!=NULL || scc_sib1!=NULL,"We need one serving cell config common\n");
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const int mu = scc ? scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing :
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scc_sib1->uplinkConfigCommon->initialUplinkBWP.genericParameters.subcarrierSpacing;
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NR_TDD_UL_DL_Pattern_t *tdd = NULL;
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if (scc && scc->tdd_UL_DL_ConfigurationCommon) {
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tdd = &scc->tdd_UL_DL_ConfigurationCommon->pattern1;
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} else if (scc_sib1 && scc_sib1->tdd_UL_DL_ConfigurationCommon) {
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tdd = &scc_sib1->tdd_UL_DL_ConfigurationCommon->pattern1;
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}
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/* Uplink symbols are at the end of the slot */
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int symb_ulMixed = 0;
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int nr_mix_slots = 0;
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int nr_slots_period = n;
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if (tdd) {
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symb_ulMixed = ((1 << tdd->nrofUplinkSymbols) - 1) << (14 - tdd->nrofUplinkSymbols);
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nr_mix_slots = tdd->nrofDownlinkSymbols != 0 || tdd->nrofUplinkSymbols != 0;
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nr_slots_period /= get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity);
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if (tdd->nrofUplinkSymbols > 1) { // if there is uplink symbols in mixed slot
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int nr_slots_period = n/get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity);
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if ((slot%nr_slots_period) == tdd->nrofUplinkSlots)
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return 1;
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}
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}
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else
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// if TDD configuration is not present and the band is not FDD, it means it is a dynamic TDD configuration
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AssertFatal(nrmac->common_channels->frame_type == FDD,"Dynamic TDD not handled yet\n");
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const struct NR_PUCCH_Config__resourceToAddModList *resList = ubwp->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList;
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// for the moment, just block any symbol that might hold a PUCCH, regardless
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// of the RB. This is a big simplification, as most RBs will NOT have a PUCCH
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// in the respective symbols, but it simplifies scheduling
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uint16_t symb_pucch = 0;
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for (int i = 0; i < resList->list.count; ++i) {
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const NR_PUCCH_Resource_t *resource = resList->list.array[i];
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int nrofSymbols = 0;
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int startingSymbolIndex = 0;
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switch (resource->format.present) {
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case NR_PUCCH_Resource__format_PR_format0:
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nrofSymbols = resource->format.choice.format0->nrofSymbols;
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startingSymbolIndex = resource->format.choice.format0->startingSymbolIndex;
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break;
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case NR_PUCCH_Resource__format_PR_format1:
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nrofSymbols = resource->format.choice.format1->nrofSymbols;
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startingSymbolIndex = resource->format.choice.format1->startingSymbolIndex;
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break;
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case NR_PUCCH_Resource__format_PR_format2:
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nrofSymbols = resource->format.choice.format2->nrofSymbols;
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startingSymbolIndex = resource->format.choice.format2->startingSymbolIndex;
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break;
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case NR_PUCCH_Resource__format_PR_format3:
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nrofSymbols = resource->format.choice.format3->nrofSymbols;
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startingSymbolIndex = resource->format.choice.format3->startingSymbolIndex;
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break;
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case NR_PUCCH_Resource__format_PR_format4:
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nrofSymbols = resource->format.choice.format4->nrofSymbols;
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startingSymbolIndex = resource->format.choice.format4->startingSymbolIndex;
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break;
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default:
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AssertFatal(0, "found NR_PUCCH format index %d\n", resource->format.present);
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break;
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}
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symb_pucch |= ((1 << nrofSymbols) - 1) << startingSymbolIndex;
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}
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/* check that TDA index 1 fits into UL slot and does not overlap with PUCCH */
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const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
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const NR_PUSCH_TimeDomainResourceAllocation_t *tdaP_UL = tdaList->list.array[0];
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const int k2 = get_K2(scc, scc_sib1, (NR_BWP_Uplink_t*)ubwp,0, mu);
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int start, len;
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SLIV2SL(tdaP_UL->startSymbolAndLength, &start, &len);
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const uint16_t symb_tda = ((1 << len) - 1) << start;
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// check whether PUCCH and TDA overlap: then, we cannot use it. Note that
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// here we assume that the PUCCH is scheduled in every slot, and on all RBs
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// (which is mostly not true, this is a simplification)
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AssertFatal((symb_pucch & symb_tda) == 0, "TDA index 0 for UL overlaps with PUCCH\n");
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// get largest time domain allocation (TDA) for UL slot and UL in mixed slot
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int tdaMi = -1;
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if (nr_mix_slots>0) {
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const NR_PUSCH_TimeDomainResourceAllocation_t *tdaP_Mi = tdaList->list.array[1];
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AssertFatal(k2 == get_K2(scc, scc_sib1, (NR_BWP_Uplink_t*)ubwp, 1, mu),
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"scheduler cannot handle different k2 for UL slot (%d) and UL Mixed slot (%ld)\n",
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k2,
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get_K2(scc, scc_sib1, (NR_BWP_Uplink_t*)ubwp, 1, mu));
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SLIV2SL(tdaP_Mi->startSymbolAndLength, &start, &len);
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const uint16_t symb_tda_mi = ((1 << len) - 1) << start;
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// check whether PUCCH and TDA overlap: then, we cannot use it. Also, check
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// whether TDA is entirely within mixed slot, UL. Note that here we assume
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// that the PUCCH is scheduled in every slot, and on all RBs (which is
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// mostly not true, this is a simplification)
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if ((symb_pucch & symb_tda_mi) == 0 && (symb_ulMixed & symb_tda_mi) == symb_tda_mi) {
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tdaMi = 1;
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} else {
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LOG_E(NR_MAC,
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"TDA index 1 UL overlaps with PUCCH or is not entirely in mixed slot (symb_pucch %x symb_ulMixed %x symb_tda_mi %x), won't schedule UL mixed slot\n",
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symb_pucch,
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symb_ulMixed,
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symb_tda_mi);
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}
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}
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nrmac->preferred_ul_tda[bwp_id] = malloc(n * sizeof(*nrmac->preferred_ul_tda[bwp_id]));
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for (int slot = 0; slot < n; ++slot) {
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const int sched_slot = (slot + k2) % n;
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nrmac->preferred_ul_tda[bwp_id][slot] = -1;
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if (frame_type == FDD || sched_slot % nr_slots_period >= tdd->nrofDownlinkSlots + nr_mix_slots)
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nrmac->preferred_ul_tda[bwp_id][slot] = 0;
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else if (nr_mix_slots && sched_slot % nr_slots_period == tdd->nrofDownlinkSlots)
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nrmac->preferred_ul_tda[bwp_id][slot] = tdaMi;
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LOG_D(MAC, "DL slot %d UL slot %d preferred_ul_tda %d\n", slot, sched_slot, nrmac->preferred_ul_tda[bwp_id][slot]);
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}
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if (tdd && k2 < tdd->nrofUplinkSlots) {
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LOG_W(NR_MAC,
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"k2 %d < tdd->nrofUplinkSlots %ld: not all UL slots can be scheduled\n",
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k2,
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tdd->nrofUplinkSlots);
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}
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return 0; // if FDD or not mixed slot in TDD, for now use default TDA (TODO handle CSI-RS slots)
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}
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// For both UL-SCH except:
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@@ -961,7 +848,7 @@ bool allocate_ul_retransmission(module_id_t module_id,
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{
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const int CC_id = 0;
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gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
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const NR_ServingCellConfigCommon_t *scc = nr_mac->common_channels[CC_id].ServingCellConfigCommon;
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NR_ServingCellConfigCommon_t *scc = nr_mac->common_channels[CC_id].ServingCellConfigCommon;
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NR_UE_info_t *UE_info = &nr_mac->UE_info;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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NR_sched_pusch_t *retInfo = &sched_ctrl->ul_harq_processes[harq_pid].sched_pusch;
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@@ -980,7 +867,7 @@ bool allocate_ul_retransmission(module_id_t module_id,
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const uint16_t bwpSize = NRRIV2BW(genericParameters->locationAndBandwidth, MAX_BWP_SIZE);
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const uint8_t nrOfLayers = 1;
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const uint8_t num_dmrs_cdm_grps_no_data = (sched_ctrl->active_bwp || ubwpd) ? 1 : 2;
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const int tda = sched_ctrl->active_ubwp ? RC.nrmac[module_id]->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot] : 0;
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const int tda = set_ul_tda(nr_mac, scc, slot);
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LOG_D(NR_MAC,"retInfo->time_domain_allocation = %d, tda = %d\n", retInfo->time_domain_allocation, tda);
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LOG_D(NR_MAC,"num_dmrs_cdm_grps_no_data %d, tbs %d\n",num_dmrs_cdm_grps_no_data, retInfo->tb_size);
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if (tda == retInfo->time_domain_allocation) {
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@@ -1249,7 +1136,7 @@ void pf_ul(module_id_t module_id,
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const uint8_t nrOfLayers = 1;
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const uint8_t num_dmrs_cdm_grps_no_data = (sched_ctrl->active_ubwp || ubwpd) ? 1 : 2;
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int dci_format = get_dci_format(sched_ctrl);
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const int tda = sched_ctrl->active_ubwp ? nrmac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot] : 0;
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const int tda = set_ul_tda(nrmac, scc, slot);
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if (ps->time_domain_allocation != tda
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|| ps->dci_format != dci_format
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|| ps->nrOfLayers != nrOfLayers
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@@ -1389,7 +1276,7 @@ void pf_ul(module_id_t module_id,
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const uint8_t nrOfLayers = 1;
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const uint8_t num_dmrs_cdm_grps_no_data = (sched_ctrl->active_ubwp || ubwpd) ? 1 : 2;
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int dci_format = get_dci_format(sched_ctrl);
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const int tda = sched_ctrl->active_ubwp ? nrmac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot] : 0;
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const int tda = set_ul_tda(nrmac, scc, slot);
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if (ps->time_domain_allocation != tda
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|| ps->dci_format != dci_format
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|| ps->nrOfLayers != nrOfLayers
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@@ -1482,7 +1369,7 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
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* schedule now (slot + k2 is not UL slot) */
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int UE_id = UE_info->list.head;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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const int tda = sched_ctrl->active_ubwp ? nr_mac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot] : 0;
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const int tda = set_ul_tda(nr_mac, scc, slot);
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if (tda < 0)
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return false;
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int K2 = get_K2(scc, scc_sib1, sched_ctrl->active_ubwp, tda, mu);
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@@ -523,7 +523,7 @@ uint8_t set_dl_nrOfLayers(NR_UE_sched_ctrl_t *sched_ctrl);
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int get_dci_format(NR_UE_sched_ctrl_t *sched_ctrl);
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const int set_dl_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int slot);
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void calculate_preferred_ul_tda(module_id_t module_id, const NR_BWP_Uplink_t *ubwp);
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const int set_ul_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int slot);
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bool find_free_CCE(module_id_t module_id, sub_frame_t slot, int UE_id);
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@@ -809,10 +809,6 @@ typedef struct gNB_MAC_INST_s {
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uint64_t dlsch_slot_bitmap[3];
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/// bitmap of ULSCH slots, can hold up to 160 slots
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uint64_t ulsch_slot_bitmap[3];
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/// Lookup for preferred time domain allocation for UL BWP, dynamically
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/// allocated. The index refers to the DL slot, and the indicated TDA's k2
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/// points to the right UL slot
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int *preferred_ul_tda[MAX_NUM_BWP];
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/// maximum number of slots before a UE will be scheduled ULSCH automatically
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uint32_t ulsch_max_frame_inactivity;
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@@ -372,38 +372,40 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
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uint8_t DELTA[4]= {2,3,4,6}; // Delta parameter for Msg3
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int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
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// UL TDA index 0 is basic slot configuration starting in symbol 0 til the last but one symbol
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struct NR_PUSCH_TimeDomainResourceAllocation *pusch_timedomainresourceallocation = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
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pusch_timedomainresourceallocation->k2 = CALLOC(1,sizeof(long));
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*pusch_timedomainresourceallocation->k2 = k2;
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pusch_timedomainresourceallocation->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
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pusch_timedomainresourceallocation->startSymbolAndLength = get_SLIV(0,13); // basic slot configuration starting in symbol 0 til the last but one symbol
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pusch_timedomainresourceallocation->startSymbolAndLength = get_SLIV(0,13);
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ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation);
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if(frame_type==TDD) {
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// TDD
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if(scc->tdd_UL_DL_ConfigurationCommon) {
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int ul_symb = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols;
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pusch_timedomainresourceallocation = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
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pusch_timedomainresourceallocation->k2 = CALLOC(1,sizeof(long));
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*pusch_timedomainresourceallocation->k2 = k2;
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pusch_timedomainresourceallocation->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
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pusch_timedomainresourceallocation->startSymbolAndLength = get_SLIV(14-ul_symb,ul_symb-1); // starting in fist ul symbol til the last but one
|
||||
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation);
|
||||
if (ul_symb>1) {
|
||||
// UL TDA index 1 for mixed slot (TDD)
|
||||
pusch_timedomainresourceallocation = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
|
||||
pusch_timedomainresourceallocation->k2 = CALLOC(1,sizeof(long));
|
||||
*pusch_timedomainresourceallocation->k2 = k2;
|
||||
pusch_timedomainresourceallocation->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
|
||||
pusch_timedomainresourceallocation->startSymbolAndLength = get_SLIV(14-ul_symb,ul_symb-1); // starting in fist ul symbol til the last but one
|
||||
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation);
|
||||
|
||||
// for msg3 in the mixed slot
|
||||
int nb_periods_per_frame = get_nb_periods_per_frame(scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity);
|
||||
int nb_slots_per_period = ((1<<mu) * 10)/nb_periods_per_frame;
|
||||
struct NR_PUSCH_TimeDomainResourceAllocation *pusch_timedomainresourceallocation_msg3 = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
|
||||
pusch_timedomainresourceallocation_msg3->k2 = CALLOC(1,sizeof(long));
|
||||
*pusch_timedomainresourceallocation_msg3->k2 = nb_slots_per_period - DELTA[mu];
|
||||
if(*pusch_timedomainresourceallocation_msg3->k2 < min_fb_delay)
|
||||
*pusch_timedomainresourceallocation_msg3->k2 += nb_slots_per_period;
|
||||
AssertFatal(*pusch_timedomainresourceallocation_msg3->k2<33,"Computed k2 for msg3 %ld is larger than the range allowed by RRC (0..32)\n",
|
||||
*pusch_timedomainresourceallocation_msg3->k2);
|
||||
pusch_timedomainresourceallocation_msg3->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
|
||||
pusch_timedomainresourceallocation_msg3->startSymbolAndLength = get_SLIV(14-ul_symb,ul_symb-1); // starting in fist ul symbol til the last but one
|
||||
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation_msg3);
|
||||
// UL TDA index 2 for msg3 in the mixed slot (TDD)
|
||||
int nb_periods_per_frame = get_nb_periods_per_frame(scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity);
|
||||
int nb_slots_per_period = ((1<<mu) * 10)/nb_periods_per_frame;
|
||||
struct NR_PUSCH_TimeDomainResourceAllocation *pusch_timedomainresourceallocation_msg3 = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
|
||||
pusch_timedomainresourceallocation_msg3->k2 = CALLOC(1,sizeof(long));
|
||||
*pusch_timedomainresourceallocation_msg3->k2 = nb_slots_per_period - DELTA[mu];
|
||||
if(*pusch_timedomainresourceallocation_msg3->k2 < min_fb_delay)
|
||||
*pusch_timedomainresourceallocation_msg3->k2 += nb_slots_per_period;
|
||||
AssertFatal(*pusch_timedomainresourceallocation_msg3->k2<33,"Computed k2 for msg3 %ld is larger than the range allowed by RRC (0..32)\n",
|
||||
*pusch_timedomainresourceallocation_msg3->k2);
|
||||
pusch_timedomainresourceallocation_msg3->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
|
||||
pusch_timedomainresourceallocation_msg3->startSymbolAndLength = get_SLIV(14-ul_symb,ul_symb-1); // starting in fist ul symbol til the last but one
|
||||
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation_msg3);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user