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@@ -392,7 +392,7 @@ void schedule_ue_spec(module_id_t module_idP,
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uint8_t dl_pow_off[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
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unsigned char rballoc_sub_UE[MAX_NUM_CCs][NUMBER_OF_UE_MAX][N_RBG_MAX];
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uint16_t pre_nb_available_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
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int mcs;
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int mcs,mcs2;
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uint16_t min_rb_unit[MAX_NUM_CCs];
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short ta_update = 0;
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eNB_MAC_INST *eNB = &eNB_mac_inst[module_idP];
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@@ -1093,6 +1093,122 @@ void schedule_ue_spec(module_id_t module_idP,
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}
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}
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break;
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case 3:
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if (frame_parms[CC_id]->frame_type == TDD) {
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switch (frame_parms[CC_id]->N_RB_DL) {
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case 6:
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->rv1 = 0;
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// deactivate TB2
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->rv2 = 1;
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->dai = (UE_list->UE_template[CC_id][UE_id].DAI-1)&3;
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break;
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case 25:
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->rv1 = 0;
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->dai = (UE_list->UE_template[CC_id][UE_id].DAI-1)&3;
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// deactivate TB2
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->rv2 = 1;
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LOG_D(MAC,"Format1 DCI: harq_pid %d, ndi %d\n",harq_pid,((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->ndi1);
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break;
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case 50:
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->rv1 = 0;
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->dai = (UE_list->UE_template[CC_id][UE_id].DAI-1)&3;
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// deactivate TB2
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->rv2 = 1;
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break;
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case 100:
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->rv1 = 0;
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->dai = (UE_list->UE_template[CC_id][UE_id].DAI-1)&3;
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// deactivate TB2
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->rv2 = 1;
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break;
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default:
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->rv1 = 0;
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->dai = (UE_list->UE_template[CC_id][UE_id].DAI-1)&3;
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// deactivate TB2
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->rv2 = 1;
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break;
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}
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}
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else {
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switch (frame_parms[CC_id]->N_RB_DL) {
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case 6:
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((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->rv1 = 0;
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// deactivate TB2
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((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->rv2 = 1;
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break;
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case 25:
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->rv1 = 0;
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// deactivate TB2
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->rv2 = 1;
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break;
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case 50:
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((DCI2A_10MHz_2A_FDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_10MHz_2A_FDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_10MHz_2A_FDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_10MHz_2A_FDD_t*)DLSCH_dci)->rv1 = 0;
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// deactivate TB2
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((DCI2A_10MHz_2A_FDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_10MHz_2A_FDD_t*)DLSCH_dci)->rv2 = 1;
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break;
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case 100:
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((DCI2A_20MHz_2A_FDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_20MHz_2A_FDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_20MHz_2A_FDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_20MHz_2A_FDD_t*)DLSCH_dci)->rv1 = 0;
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// deactivate TB2
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((DCI2A_20MHz_2A_FDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_20MHz_2A_FDD_t*)DLSCH_dci)->rv2 = 1;
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break;
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default:
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->mcs1 = mcs;
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->harq_pid = harq_pid;
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->ndi1 = 1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->rv1 = 0;
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// deactivate TB2
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->mcs2 = 0;
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->rv2 = 1;
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break;
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}
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}
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break;
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case 4:
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// if (nb_rb>10) {
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((DCI2_5MHz_2A_TDD_t*)DLSCH_dci)->mcs1 = mcs;
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@@ -1860,6 +1976,91 @@ void fill_DLSCH_dci(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP
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0);
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break;
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case 3:
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LOG_D(MAC,"[eNB %d] Adding Format 2A UE %d spec DCI for %d PRBS (rb alloc: %x) \n",module_idP, UE_id, nb_rb,rballoc);
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if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
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switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
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case 6:
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->rah = 0;
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size_bytes = sizeof(DCI2A_1_5MHz_2A_TDD_t);
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size_bits = sizeof_DCI2A_1_5MHz_2A_TDD_t;
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break;
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case 25:
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->rah = 0;
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size_bytes = sizeof(DCI2A_5MHz_2A_TDD_t);
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size_bits = sizeof_DCI2A_5MHz_2A_TDD_t;
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break;
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case 50:
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_10MHz_2A_TDD_t*)DLSCH_dci)->rah = 0;
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size_bytes = sizeof(DCI2A_10MHz_2A_TDD_t);
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size_bits = sizeof_DCI2A_10MHz_2A_TDD_t;
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break;
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case 100:
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_20MHz_2A_TDD_t*)DLSCH_dci)->rah = 0;
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size_bytes = sizeof(DCI2A_20MHz_2A_TDD_t);
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size_bits = sizeof_DCI2A_20MHz_2A_TDD_t;
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break;
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default:
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_5MHz_2A_TDD_t*)DLSCH_dci)->rah = 0;
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size_bytes = sizeof(DCI2A_5MHz_2A_TDD_t);
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size_bits = sizeof_DCI2A_5MHz_2A_TDD_t;
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break;
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}
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}
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else {
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switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
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case 6:
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((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->rah = 0;
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size_bytes=sizeof(DCI2A_1_5MHz_2A_FDD_t);
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size_bits=sizeof_DCI2A_1_5MHz_2A_FDD_t;
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break;
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case 25:
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->rah = 0;
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size_bytes=sizeof(DCI2A_5MHz_2A_FDD_t);
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size_bits=sizeof_DCI2A_5MHz_2A_FDD_t;
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break;
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case 50:
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((DCI2A_10MHz_2A_FDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_10MHz_2A_FDD_t*)DLSCH_dci)->rah = 0;
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size_bytes=sizeof(DCI2A_10MHz_2A_FDD_t);
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size_bits=sizeof_DCI2A_10MHz_2A_FDD_t;
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break;
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case 100:
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((DCI2A_20MHz_2A_FDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_20MHz_2A_FDD_t*)DLSCH_dci)->rah = 0;
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size_bytes=sizeof(DCI2A_20MHz_2A_FDD_t);
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size_bits=sizeof_DCI2A_20MHz_2A_FDD_t;
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break;
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default:
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
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((DCI2A_5MHz_2A_FDD_t*)DLSCH_dci)->rah = 0;
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size_bytes=sizeof(DCI2A_5MHz_2A_FDD_t);
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size_bits=sizeof_DCI2A_5MHz_2A_FDD_t;
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break;
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}
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}
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add_ue_spec_dci(DCI_pdu,
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DLSCH_dci,
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rnti,
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size_bytes,
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process_ue_cqi (module_idP,UE_id),//aggregation,
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size_bits,
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format2A,
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0);
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break;
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case 4:
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//if (nb_rb>10) {
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