 ChiehChun
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a8cc08ace5
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Cannot allocate CCE error -> debug message
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2021-02-07 10:45:57 +01:00 |
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ChiehChun
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8a823d22cf
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Better format dump_mac_stats()
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2021-02-07 10:45:57 +01:00 |
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ChiehChun
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c51cb3f40b
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Enable 2 UL slots
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2021-02-07 10:45:57 +01:00 |
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ChiehChun
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8bf2d1a12f
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Remove assert of allocate CSI PUCCH
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2021-02-07 10:45:57 +01:00 |
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ChiehChun
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fde6c46ef1
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Remove assertion for single UE
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2021-02-07 10:45:57 +01:00 |
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ChiehChun
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14614d74cf
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Find max coeff & Decrease n_rb_sched
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2021-02-07 10:45:57 +01:00 |
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ChiehChun
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56831038d0
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Check BSR & Create UE_sched for UL new transmission
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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1b1411727c
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Calculate UL throughput & Initial ulsch_current_bytes
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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cf725a1801
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Create find_CCE in primitive
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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bec348405b
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Find the largest contiguos region
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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8f988e384d
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Add pf_ul & pseudo code
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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5573b8e18c
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Change vrb_map_UL to rballoc_mask
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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2becbb9210
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Verify the same K2
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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7da43c95d2
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Change pre_precessor_ul type to bool
- To check the current slot is the scheduled slot(UL slot - K2) and
only execute the post processor in scheduled slot.
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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0234015f8e
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Check slot is DL slot to pre-schedule UL data
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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2283e12560
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Calculate rbSize from estimated buffer
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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c7ffd5740f
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Add sched_ul_bytes/ulsch_current_bytes & Update in rx_sdu/schedule_ulsch
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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4d0a2e4877
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Save selected UL HARQ PID in post-processor
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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989aade7b8
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Log lcid default case & pirntout MAC PDU
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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21e9339427
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Add short/long BSR Table & Log the BSR value
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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c316f2fc57
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Correct bit ordering in struct NR_BSR_LONG
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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a95346d169
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Modify the case of truncated BSR
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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1ff770ff20
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Add CE & BSR pointer
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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2b6a651aae
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Fix LCID of CRNTI for nr UE
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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5e226b9e22
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Remove assertion for single UE
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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3bb4bddc0d
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Allocate DL new transmission
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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a7cb83889a
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Find max coeff from UE_sched
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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6d5634b8ce
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Check DL buf and Calculate the coeff to create UE_sched
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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a3cc9f730b
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Add dlsch_current_bytes and Calculate throughput
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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0dd0f5ce4a
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Create function for find CCE and retransmission
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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13da3d6e8a
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Create nr_store_dlsch_buffer()
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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68b03e9cb6
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Create pf_dl function
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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3b4ec2c82b
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Change vrb_map to rballoc_mask
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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6c3897d4a7
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Save selected DL HARQ PID in post-processor
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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9fb45867a1
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Initial num_pdcch_cand for multi-UE
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2021-02-07 10:39:40 +01:00 |
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ChiehChun
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62c58bd722
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Use correct pucch_index_used
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2021-02-07 10:39:39 +01:00 |
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