newly-generated files for innermost part of the parity bit
generation which, for AVX512, uses the mm512_permutex2var_epi8
instruction and for 128-bit (aarch64) the mm_alignr_epi8 (vextq_s8) in
the computation corresponding to each non-zero bit of the H matrix.
It is generated with ldpctest -n0 -g1. the changes for this are in a
future MR. I did these changes to compare with the GPU version
(ldpc_encoder_cuda), so that the CPU version is as fast as possible. The
generator will come when we merge the GPU encoder/decoder which also has
a generator for the CUDA version. it was difficult to extract the
changes in ldpctest/ldpc_encoder.c so I just took the generated file.
This allows for removing a very large memcpy and reduces the memory
demand for the parity matrix computation. For the moment this is limited
to largest case in BG1, namely Zc=384. This is the only format used when
the number of segments after codeblock segmentation is large (>8). This
improves the timing required for ldpc parity bits generation by more
than a factor 2 with AVX512. This significantly reduces the total time
to generate the DLSCH/PDSCH
1. 3GPP Rate-matching/interleaving on 8-segment blocks, deinterleaving at output of multi-segment processing.
2. Bit-packing done in nrLDPC_coding_segment_encoder.c now instead of nr_scrambling.
Interestingly, it improves performance significantly too.
Tested for AVX512 only for now.
Avoid the use of simde_mm_sign_epi8 which is inefficient on aarch64.
Decoding times are significantly improved on aarch64.
Co-authored-by: Romain Beurdouche <romain.beurdouche@eurecom.fr>
which will drop PUCCH 2 indications that are detected as DTX. For the
moment this uses the same pucch0_dtx_threshold value indicated in L1
section of the configuration file.
fixes the overflow issue in the PUCCH2 RX with 4+ RX antennas and 12+
bits (polar code format). The fix scales the polar decoding LLR
computation according to the number of RX antennas. The issue was clear
for 100 MHz 4 RX antennas. Even
nr_pucchsim -s -5 -q 8 -P 2 -b 12 -R 273 -z4 -n1000
doesn't converge to 0 BLER with increasing SNR. The issue didn't appear
in CI because of the bandwidth and antenna count limitations.
This commit introduces a separate thread (l1_tx_thread) that processes
gNB DL/TX slots. It receives a message from the ru_thread when a new
slot started, and starts processing.
The DL part of the scheduler is run in the l1_tx_thread. Therefore,
only call UL indication (for scheduler) in UL slots. The UL indication
previously triggered the DL scheduler -- hence, it had to be called in
every slot. Now, since the DL scheduler is moved into the DL thread, we
don't have to call the scheduler in every slot anymore.
The reorder thread is removed, as reordering with this scheme is not
necessary anymore.
The main advantage of this version is that the TX can be scheduled
earlier (sl_ahead). Further, there can no longer be race conditions in
the TX path, since the scheduler/L2, TX L1 processing and the RU tx
function are all execute in the same thread (L1_tX_thread).
Also, the scheduler prepares PRACH/PUSCH/PUCCH FAPI PDUs. As of this
commit, the scheduler runs in the TX processing chain, whereas these
PDUs are destined for RX processing. Thus, too avoid data races,
instead of triggering the RX processing at the same time as TX
processing in the RU thread, this commit changes the code to trigger RX
processing after the scheduler has been run in TX processing to avoid
data races.
Finally, we synchronize RU and L1 threads. This is important for
rfsimulator, since unlike most radios, rfsimulator can run slower or
faster, depending on I/O and CPU (it does not have a stable "tick").
Co-authored-by: kiran <saikiran@iitj.ac.in>
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.
- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
optimizations for 128-bit to improve performance of LDPC encode/decode
on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
Provides the backoff from full-scale output at the L1 entity
(frequency-domain samples). Default is, 36 dBFS, which is the correct
value when using the OAI RU entity. For O-RAN RU, this value should be
set according to the O-RU manufacturer requirements. For example 12
would corresponding to 14-bit input level (6 dB/bit).
Applies the TX amp backoff to PBCH, PDCCH and CSI
reorder_thread_disable we use the native message queue and L1_rx_thread instead of the thread-pool for the main L1 thread. There is a single TX thread (no slot parallelization)
the SDU has this size the function will return. This is an old piece of
code where 255 meant -1 which was what was returned from the asn1c
encoding function if the ASN.1 message was not encodable.
To SIB2 and its passing to RRC. Parameter was read but not transfered
before. Basic LTE-M functionality should ok on develop branch with this
fix. Tested with uBlox SARA-R4 (QCOM chipset)
-After that no DL traffic is getting blocked at the Accelleran CU for low values of throughput
-Remaining to remove the hardcoded value of buffer availability and report the actual value from the DU.
Raymond Knopp